[SI-LIST] Re: SDRAM Routing Topology - Follow Up
- From: Kevin K <khai77069@xxxxxxxxx>
- To: "Moran, Brian P" <brian.p.moran@xxxxxxxxx>, weirsi@xxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Sat, 15 Jul 2006 17:23:21 -0700 (PDT)
Brian,
I'm working with SDR SDRAM. The clocks and DQS
signals are T routed. The signals I have questions on
are Adddr/Control and DQ signals.
Thank you,
Kevin
--- "Moran, Brian P" <brian.p.moran@xxxxxxxxx> wrote:
> Kevin,
>
> One thing I forgat to mention is if you are talking
> about dasy chaining
> CTRL and ADR/CMD,
> you may be forced to dasiy chain CLK in order to
> keep the setup and hold
> timing in spec.
> Can't say for sure becasue I have not ever tried it.
> If you do daisy
> chain CLK, then
> you have all sorts of problems with the strobe to
> CLK setup and hold
> timing. So again,
> my inclination would be the Tee topology.
>
>
> Brian P. Moran
> MPG Advanced Platform Engineering
> Intel Corporation
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Kevin K
> Sent: Saturday, July 15, 2006 1:43 PM
> To: weirsi@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: SDRAM Routing Topology
>
> Steve,
> You're right.
> The address and control lines go to all four
> SDRAM's.
> When I tried to use T topology, but it's very
> difficult to length match
> all four branches of the T.
> I'm now trying daisy-chain topology, it's easier to
> route and there're
> not branches of the T to match, but the trace
> lengths are longer than T
> topology. I will have to run some simulations.
> Which topology do most people use?
> Has anybody had any timing issues with a design
> using daisy-chain
> topology (since the traces are long)?
>
> Thank you,
> Kevin
>
> --- steve weir <weirsi@xxxxxxxxxx> wrote:
>
> > Kevin, it doesn't sound like you have a simulator.
>
> > A T topology will
> > get into trouble pretty quickly I advise against
> it.
> > A simulator
> > would tell you if you can get away with what you
> would like.
> >
> > Steve
> > At 07:34 AM 7/1/2006, Kevin K wrote:
> > >Dear Experts,
> > >I'm working on a design that uses the PPC405EP
> > (Power
> > >PC). The memory subsystem consists of four SDR
> SDRAM's. What's the
> > >SDRAM routing topology?
> > >1) Daisy-chain topology
> > >2) T-topology
> > >3) Either topology as long as the length
> > requirements
> > >are met.
> > >
> > >I have a reference design board that uses both
> daisy-chain topology
> > >and T-topology.
> > >
> > >Thank you,
> > >Kevin
> > >
> > >
> >
> >__________________________________________________
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