[SI-LIST] Re: SDRAM Routing Topology
- From: Kevin K <khai77069@xxxxxxxxx>
- To: weirsi@xxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Sat, 15 Jul 2006 13:42:44 -0700 (PDT)
Steve,
You're right.
The address and control lines go to all four SDRAM's.
When I tried to use T topology, but it's very
difficult to length match all four branches of the T.
I'm now trying daisy-chain topology, it's easier to
route and there're not branches of the T to match, but
the trace lengths are longer than T topology. I will
have to run some simulations.
Which topology do most people use?
Has anybody had any timing issues with a design using
daisy-chain topology (since the traces are long)?
Thank you,
Kevin
--- steve weir <weirsi@xxxxxxxxxx> wrote:
> Kevin, it doesn't sound like you have a simulator.
> A T topology will
> get into trouble pretty quickly I advise against it.
> A simulator
> would tell you if you can get away with what you
> would like.
>
> Steve
> At 07:34 AM 7/1/2006, Kevin K wrote:
> >Dear Experts,
> >I'm working on a design that uses the PPC405EP
> (Power
> >PC). The memory subsystem consists of four SDR
> >SDRAM's. What's the SDRAM routing topology?
> >1) Daisy-chain topology
> >2) T-topology
> >3) Either topology as long as the length
> requirements
> >are met.
> >
> >I have a reference design board that uses both
> >daisy-chain topology and T-topology.
> >
> >Thank you,
> >Kevin
> >
> >
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