[SI-LIST] Re: Routing and diff via pairs
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: Aubrey Sparkman <asparkman@xxxxxxxxxxxxx>
- Date: Tue, 15 Sep 2009 13:30:18 -0400
Aubrey
It all depends on where the grounds are, now doesn't it.
call me
Scott
--
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC
Aubrey Sparkman wrote:
> All,
> I had in interesting idea proposed to be my our layout guy -- he said the
> routing would go faster if he could place transition vias on 50 mil centers.
> Our board is 110 mils thick, 20 layers, 2 microstrip, 6 internal stripline
> routing layers.
> I'm interested in your thoughts on comparing 2 cases -- Scenario B where the
> diff pair transition vias are on a 50 mil grid and Scenario C where the via
> pairs are on 30 mil centers with 90 mils center to center between two
> different pairs. In both cases, 150 mils center to center of outer vias.
>
> Text graphic attempt to show via locations:
> p n p n
> Scenario B: O O O O
>
> p n p n
> Scenario C: O O O O
>
> The diff pairs involved are PCIe Gen2 and the 100MHz PCIe Ref Clks.
>
> In Scenario B, the diff pairs on layer Y route between the P and N vias
> transtioning from layer X to layer Z and there is always more than 40 mils
> between diff pairs.
> pn pn pn
> p | | n | | p | | n
> Scenario B: O | | O | | O | | O
> | | | | | |
>
> In Scenario C, the diff pairs on layer Y do not route between the P and N
> vias transtioning from layer X to layer Z but the gap between the diff pairs
> goes down to 10 mils to get between the via pairs.
>
> pn pn pn
> | | | | | |
> | | | | | |
> p n | | | | | | p n
> Scenario C: O O | | | | | | O O
> | | | | | |
> | | | | | |
> | | | | | |
>
> Comments?
>
> Aubrey Sparkman
> 512-461-6165
> Aubrey.K.Sparkman@xxxxxxxx
>
>
>
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