[SI-LIST] Re: Rocket I/O pcb layout
- From: "Hargin, Bill" <bill_hargin@xxxxxxxxxxx>
- To: <l_alexman@xxxxxxxxxxxxxxxxxxxx>, "Si-List" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 22 Dec 2004 11:04:05 -0800
Hi Leonard:
> I am doing a PCB Layout using Xilinx's Rocket I/O chips. I=20
> have read a lot about signal integrity from the Xilinx's web=20
> site and even got DR Johnson's DVD on rocket IO which is a=20
> great DVD but, not being an SI expert, I have a few questions=20
> that perhaps someone could explain or point me into the right=20
> direction to an article I could read? I appreciate any help=20
> you could provide.
There's a new RocketIO design kit for HyperLynx GHz on
http://www.mentor.com/products/pcb/pads/design_kits/hl-rocketio_design_k
it.cfm. I believe it would help you experiment around enough to answer
most of the questions you've listed below and more. A couple of
caveats: a) The kits are currently based around pre-layout schematics;
and some of yoru questions would require pulling in an actual foard
file. (Easy to do.) b) To simulate an actual design, you'll need the
released software (v7.2) or the v7.5 beta. (Contact me offline if you
want to apply as a beta site. We're interested in getting a few more
RocketIO customers on the beta for 7.5.)
General comments below. (Simulation or test boards are advised to get
"real" answers here ... To augment the generalized advice you're likely
to get.)
> 1. I have seen on DR Johnson's DVD how the eye pattern looks=20
> on one side of the signal and then 26 inches later how much=20
> smaller it looks and the receiver still works. My question is=20
> that FR4 material has a delay about 1.8 NS per foot. At 26=20
> inches across two cards and a backplane, doesn't the 4=20
> nanoseconds of delay in the fr4 material exceed the signal=20
> speed in the Gigahertz range (1 nanosecond) or is it these=20
> drivers and receivers work differently then lets say standard=20
> TTL signals?
With SERDES designs, delay, which is a big factor for synchronous
signals, takes a back seat to loss, both dielectric loss and (resistive)
skin effects. The closure of the eye being the big issue.
> 2. In a perfect design signals would go from the BGA at 100=20
> ohms to perfect vias to the bottom of the board to perfect=20
> 100-ohm traces to a connector. I have a few questions about=20
> what to do in a non-perfect design.
>=20
> a. On connections to the BGA pins I can use the standard dog=20
> bone pattern and have the vias 40 mils from the bga pins but=20
> the traces are not going to be next to each other to form 100=20
> ohm differential in this short space. Is it acceptable to do=20
> this since or should I route the traces from the bga pads to=20
> vias further away from the BGA where I can route the traces=20
> as differential pairs?
This is a common problem when fanning out from a BGA. As long as
overall path lengths are matched, and crosstalk with adjacent aggressors
is considered (using common sense and simulating).
> b. I have not seen anything that talks about if there are=20
> any requirements for the spacing between the two vias on a=20
> differential pair or how to calculate the impedance of a via.=20
> I know having a larger antipad on the plane layers helps but=20
> what about spacing between the vias? Or the fact that the gap=20
> between the traces changes going into the two vias?
Keep in mind that vias - generally speaking - do bad things to
super-high-speed signals, so the fewer the better. HyperLynx GHz
simulates the impact of vias on signal/eye quality, and v7.5 includes a
"Via Visualizer" capability that you may find handy, as far as looking
at via parasitics (L, C, Z0, Td, etc.).=20
> c. I have set up a 30-mil edge-to-edge gap between all rocket=20
> IO differential pairs to reduce the crosstalk but at the=20
> connector area I can get many more traces routed on a bottom=20
> layer if I violate the 30-mil spacing for about 500 mils to=20
> about 5 mil Gap instead of the 30 mil. Would this cause any=20
> crosstalk problems since its such a short trace?
It will cause some crosstalk ... The question is whether the crosstalk
will be significant enough to cause a problem at the receiver. Again,
this is where simulation of your actual layout would be necessary,
rather than relying on overly-simplified design rules.
> d. In order to match the lengths of the differential pair I=20
> usually extend one of the traces at either the connector end=20
> or the last via and wrap the trace around the pin or via to=20
> get additional length. Are there any problems with this=20
> method? Is there another method that is better ?
If you wrap in the same direction, self-coupling can be the problem
here. The severity of the potential problem depends on how clean your
eye is in the first place, and the parallel length over which the
self-coupling occurs. To mitigate this effect, it's better to take a
non-parallel routing path to avoid the self-coupling problem.
Bill Hargin
Product Manager - HyperLynx
Mentor Graphics Corp.
425-497-5079 - Direct
425-301-4425 - Mobile
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