[SI-LIST] Re: Rocket I/O pcb layout
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: l_alexman@xxxxxxxxxxxxxxxxxxxx
- Date: Wed, 22 Dec 2004 13:49:19 -0500
Leonard
Here are a few answers to your questions, however I would highly
recommend that you engage the services of someone that has done this a
few times. Differential signaling can be quite robust, as Xilinx and
Dr. Johnson indicate. It is the details that either make or break a design.
1) PCB traces act as transmission lines that are capable of storing
multiple bits in a data stream. It is not the delay that is important,
but the loss.
2a) Differential coupling on any edge coupled differential pair is quite
weak. It is permissible to break differential spacing rules in
breakout. However, there are optimal and not-so-optimal ways to do this
that can either enhance or reduce overall performance.
2b) There is actually quite a bit of information about differential via
spacing and design out there. If I recall, there is an Ansoft article
on this for small form factor plugable connectors. However,
differential via design is dependent upon the via diameter, the pad
diameter, the via-to-via pitch, the antipad diameter and type
(dual-circular, single-rectangular, single-oval ...) etc, trace width,
stackup, and trace layer entry and exit. Normally, we design and
optimize using a full wave field solver, CST Microwave Studio.
2c) Breaking your spacing rule should be done in conjunction with
simulation of the coupling in the channel. 500 mils may sound like a
short distance, but electrically it is approximately 75 to 90 ps long.
Depending upon the edge speed of the drivers, this may be enough coupled
length to develop significant crosstalk. In many designs i have seen,
it is not loss but crosstalk that limits performance. This crosstalk
comes from the connectors, the packages, the breakout vias, the
transition vias and the traces. All need to be looked at as a
synergistic whole. We've done a lot of work with Samtec on their Final
Inch(TM) designs for multiple connector families, including some surface
mount BGA-style connectors, where we have completely modeled and
simulated the breakout regions, vias, and differential traces. This is
not a trivial task.
2d) Length matching of differential pairs is an interesting topic in
light of the nature of FR4 laminate construction. It is my contention
that extreme measures for length matching of differential pairs come to
naught, unless in matching and skew control due engineering
consideration is given to the nature of epoxy/fiberglass laminate
weaves. Teraspeed Consulting will be presenting a paper at DesignCon
2005 on this very topic, titled:
"The Impact of PCB Laminate Weave on the Electrical Performance of
Differential Signaling at Mutli-Gigabit
Data Rates"
Another paper we are delivering is especially germane to FPGA design:
"High Performance FPGA Bypass Filter Networks"
best regards,
scott
-
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
(503) 750-6481 Cellular
http://www.teraspeed.com
Teraspeed is the registered service mark of
Teraspeed Consulting Group LLC
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