[SI-LIST] Rocket I/O pcb layout
- From: "Leonard Alexman" <l_alexman@xxxxxxxxxxxxxxxxxxxx>
- To: "Si-List" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 22 Dec 2004 09:14:34 -0800
Hello all you SI experts.
I am doing a PCB Layout using Xilinx's Rocket I/O chips. I have read a lot
about signal integrity from the Xilinx's web site and even got DR Johnson's
DVD on rocket IO which is a great DVD but, not being an SI expert, I have a
few questions that perhaps someone could explain or point me into the right
direction to an article I could read? I appreciate any help you could
provide.
1. I have seen on DR Johnson's DVD how the eye pattern looks on one side of
the signal and then 26 inches later how much smaller it looks and the
receiver still works. My question is that FR4 material has a delay about 1.8
NS per foot. At 26 inches across two cards and a backplane, doesn't the 4
nanoseconds of delay in the fr4 material exceed the signal speed in the
Gigahertz range (1 nanosecond) or is it these drivers and receivers work
differently then lets say standard TTL signals?
2. In a perfect design signals would go from the BGA at 100 ohms to perfect
vias to the bottom of the board to perfect 100-ohm traces to a connector. I
have a few questions about what to do in a non-perfect design.
a. On connections to the BGA pins I can use the standard dog bone pattern
and have the vias 40 mils from the bga pins but the traces are not going to
be next to each other to form 100 ohm differential in this short space. Is
it acceptable to do this since or should I route the traces from the bga
pads to vias further away from the BGA where I can route the traces as
differential pairs?
b. I have not seen anything that talks about if there are any requirements
for the spacing between the two vias on a differential pair or how to
calculate the impedance of a via. I know having a larger antipad on the
plane layers helps but what about spacing between the vias? Or the fact that
the gap between the traces changes going into the two vias?
c. I have set up a 30-mil edge-to-edge gap between all rocket IO
differential pairs to reduce the crosstalk but at the connector area I can
get many more traces routed on a bottom layer if I violate the 30-mil
spacing for about 500 mils to about 5 mil Gap instead of the 30 mil. Would
this cause any crosstalk problems since its such a short trace?
d. In order to match the lengths of the differential pair I usually extend
one of the traces at either the connector end or the last via and wrap the
trace around the pin or via to get additional length. Are there any problems
with this method? Is there another method that is better ?
TIA Leonard Alexman
Leonard Alexman / American Electronics Group Inc.
PH: 951-354-6493
Cell: 951-640-5469
Fax: 208-247-3470
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