[SI-LIST] Re: Right Angle Bends
- From: wolfgang.maichen@xxxxxxxxxxxx
- To: "Tom Dagostino" <tom@xxxxxxxxxxxxx>, leeritchey@xxxxxxxxxxxxx
- Date: Mon, 18 Jul 2011 17:19:54 -0700
Tom, Lee, all,
I did some experiments and simulations for 90 degree bends as part of my
TDR class. I just put the relevant slides online:
http://www.testtechniques.com/files/90_degree_bend.pdf
The test vehicle was a 3mm (120 mil) wide trace on a standard FR-4
substrate (62 mil thick). The capacitive dip caused by the bend is clearly
visible. Measurement (0.4pF) using a self-made TDR instrument (T20/80 ~
100ps) and simulation using Sonnet Lite (0.27pF) of the excess capacitance
are in reasonable agreement. (Note that the simulation was done for a 50
Ohm trace while the actual test vehicle turned out to be ~46.4 Ohms, which
explains at least some of the mismatch). Since the capacitance scales
linearly with feature size, the conclusion is that a "normal sized" trace
used in high-speed digital signaling - only a few mils wide - will thus
have much smaller parasitics: even at 10 mil width it would be down to
0.04pF, or a Tc of Zo/2*C < 1ps. Which is indeed negligible up to quite a
few GHz unless you have many such bends in your path (which could happen
e.g. in a serpentine line). 4mil traces are even better. Also interesting
to see (in the simulation) is the current crowding on the trace which makes
the excess area of the bend (where only little current is flowing) less of
a concern than a simple geometric consideration would suggest.
Regards,
Wolfgang
From: "Tom Dagostino" <tom@xxxxxxxxxxxxx>
To: "'Lee Ritchey'" <leeritchey@xxxxxxxxxxxxx>, "'Julian Ferry'"
<julian.ferry@xxxxxxxxxx>, "'Brad Brim'" <bradb@xxxxxxxxxxx>,
"'Jeff Walden'" <jwalden@xxxxxxxx>, <si-list@xxxxxxxxxxxxx>
Date: 07/16/2011 04:53 PM
Subject: [SI-LIST] Re: Right Angle Bends
Sent by: si-list-bounce@xxxxxxxxxxxxx
Lee
I have measured 50 Ohm traces that were on the order of 0.100" wide that
had
90 degree bends. It was very easy to point out the bend on the TDR plots.
If I can find those boards again, they are well over 10 years old, I'll
remeasure them and put out the details.
Tom Dagostino
Teraspeed Labs
9999 SW Wilshire St.
Suite 102
Portland, OR 97225
USA
971-279-5325 Office
971-279-5326 FAX
503-430-1065 Cell
tom@xxxxxxxxxxxxx
www.teraspeed.com
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
401-284-1827
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Lee Ritchey
Sent: Friday, July 15, 2011 3:32 PM
To: Julian Ferry; Brad Brim; 'Jeff Walden'; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Right Angle Bends
I've have asked for evidence that this high power microwave problem exists.
Same answer, "somebody says", nobody has shown it with measurements.
As to the paper, the simulations were not validated with any measurements.
As to the Montrose paper, refer to the 90 degree corner paper which is well
controlled laboratory measurements which contradict it.
What is true is that with very high power RF and microwave there is also
high voltage. With high voltage comes corona discharge and potential
arcing
at sharp points. That is a good reason to avoid pointy structures of any
kind in these applications. But it is not a signal integrity problem.
--------------------------------------------------
From: "Julian Ferry" <julian.ferry@xxxxxxxxxx>
Sent: Friday, July 15, 2011 12:48 PM
To: "Brad Brim" <bradb@xxxxxxxxxxx>; "'Jeff Walden'" <jwalden@xxxxxxxx>;
<si-list@xxxxxxxxxxxxx>
Subject: [SI-LIST] Re: Right Angle Bends
>
> I think one of the problems here is that like with most myths or urban
> legends, there is a kernel of truth to it.
>
> It is pure, unarguable physics that the capacitance will go down and
> the inductance will go up in a right angle bend. The question is
> whether that change matters in a particular application.
>
> For some applications, like in high power microwave or RF
> applications, this effect can be significant enough relative to other
> factors that it is definitely worth worrying about.
>
> But in the grand scheme of things in the current SI world, this change
> is way down on the list of potential problems. It is effectively
> swamped out by many other effects (like our relatively crappy
> connectors, for one
> example...)
>
> I think these guys wrote a pretty decent little paper with some math
> that can help determine whether you might need to worry about bends.
>
> http://www.millertechinc.com/pdf_files/mti_tn063_microstrip_right_angl
> e_bends.pdf
>
>
> Also keep in mind that we in the SI world are mostly dealing with
> pulsed signals, where a large portion of the energy is contained in
> the lower frequency components. The excess capacitance will only
> affect the very high frequency components. But in the microwave
> environment, it's all about the high frequency signal, so a bend can be a
much greater concern.
>
>
>
> Julian Ferry
> High Speed Engineering Manager
> Samtec, Inc
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Brad Brim
> Sent: Friday, July 15, 2011 2:57 PM
> To: 'Jeff Walden'; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Right Angle Bends
>
> exactly, Jeff ... and the traces that connect to the bends are also
> MUCH longer than typical for the RF/microwave case.
>
> In RF/mw ckt sim libraries/layouts a bend is a separate "component".
> The reference planes (i.e. where the traces connect to the bend) are
> at the edge of this component. For example, the 90-degree bend
> reference planes are at the edge of the square representing the area
> of the bend. For most SI applications the bend is NOT a separate
> component and the two traces simply meet at a single node. Having
> worked way too many hours to implement and test RF/mw ckt sim bend
> models over a dozen years ago I observed the parasitics are a delay of
> length on the order of the node-to-node distance with additional
> capacitive parasitics for sharp bends and inductive parasitics for
> aggressively chamfered bends. For a 90 degree bend the different
> definitions of reference plane imply 2*(W/2) additional length trace
> for the SI case. Given approximate parasitic delay of sqrt(2)*W/2, all
> implies doing nothing for SI applications is still on the order of
> only 30% phase delay error versus a much more precise parasitic model
> (for an already small parasitic). The phase delay dominates because
> bend capacitive parasitics are small for SI apps relative to other
> capacitive parasitics not modeled throughout the system.
>
> Therefore, if the trace are not wide (low impedance) and their lengths
> coming in/out of the bend are long relative to the linewidth, then
> ignoring the bend is obviously the correct choice.
>
> Where SI apps might not always want to ignore bends is for tight
> meander structures used to accumulate phase delay and balance skew.
> These geometries sometimes have short distance between bends and could
> therefore lose some accuracy from ignoring bend parasitics. In these
> cases it is probably more important to include coupling amongst the
> parallel traces. As we all might guess, if you need to know a meander
> behavior accurately you may wish to model it as a single component
> with more detailed simulation rather than treat it as a collection of
> traces (with or without bend parasitics).
>
> cheers,
> -Brad
>
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx
>> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Jeff Walden
>> Sent: Friday, July 15, 2011 10:55 AM
>> To: si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] Re: Right Angle Bends
>>
>> The difference is that today's SI traces are significantly narrower
>> than the typical "RF" microstrip of 30 years ago.
>> -Jeff
>>
>>
>
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