A1: Yes. For that short pulse example, the return current is a local phenomenon that travels with the forward pulse, and it will exist on both nearby planes, split according to proximity but in sum equal to the forward current. If the trace is not in isolation, some of the current will also be induced in nearby traces = crosstalk. A2: Yes, image current will exist simultaneously on every adjacent plane (split as per above), regardless of where each fits into the scheme of the PDN. The PDN design must account for this by keeping a low HF impedance between adjacent planes, not just at the power supply, but continuously along the path of each signal trace placed between them. This is done by keeping the separation small, and adding properly implemented bypass caps. In the case of diff pairs, return currents still exist to the extent that the finite distance between conductors results in image currents that are also slightly separated, and therefore sum to zero only in the aggregate. For side by side, the aggregate cancellation happens on each image plane. For over/under, the aggregate cancellation requires local current flow between planes, provided by local interplane capacitance. On Mon, 5 Nov 2007 10:03:48 -0500 "Pras venki" <venki.pras@xxxxxxxxx> writes: Thanx a lot for replying..i guess it is a bit more clear 2 me than b4... do u mean 2 say that at an instant of time the current pulse can exist on the signal trace (flowing away frm the driver) and right at that instant the 'reverse' current pulse can exist on the Vdd plane (flowing into the driver)? also that an image current can exist on the Vdd plane at the same time when the forward current is flowing (in case the forward current pulse is wide enough). Just that they have 2 sum 2 give the current actually required to charge the load (KCL)? Thanx a lot, Pras On 11/5/07, olaney@xxxxxxxx <olaney@xxxxxxxx> wrote: Others are doing a fine job of explanation, but to help clarify, keep in mind the basic principle that current can and does "flow" through insulators -- in the form of capacitance charging and discharging currents. This applies to interplane capacitance as well as discrete bypass caps. It is not necessary to think of current as arriving from and returning to the power supply unless you are at a frequency lower than the bandwidth of the regulator loop. Past a few tens of kilohertz, the PS only supplies average current, and capacitance does all the real work. The closer the capacitor is to the load, the harder it works. At high enough frequencies, even the storage caps in the power supply cease to matter. HF performance is often determined almost entirely by the capacitance in the package and within a few inches of the pin. In fact, HF currents never reach the power supply for properly designed boards, and it is not a meaningful participant in the current demands of fast edges. The term "return current" in context means reverse current flows induced by signals propagating in the forward direction. By KCL, these must sum to the same magnitude, though the finite speed of propagation means that this is on an instantaneous, local basis. For short pulses, it is possible to have current (and corresponding return current) flowing in that part of the path where the pulse is at a given instant, but zero (or some other value) on either side. The fact that the planes on either side might be at different DC potentials is irrelevant. That only enters in by way of requiring dielectric separation between layers, i.e. capacitance, however implemented. It is the adequacy of that implementation that is at issue, not whether any given plane is ground or other reference in the DC sense. The return current will split according to proximity to nearby planes without regard for the DC use of those planes. The corresponding local voltages are a matter of the impedance presented by the local PDN. Orin Laney On Sun, 4 Nov 2007 21:44:27 -0500 "Pras venki" <venki.pras@xxxxxxxxx> writes: > Hello Guys, > I have this confusion regarding "*Return currents*"- > > 1) In the paper "SSN & power plane bounce in CMOS technology" by > Larry Smith > ( http://www.csee.umbc.edu/vlsi/reports/ssn_pwr_planes.pdf > <http://www.csee.umbc.edu/vlsi/reports/ssn_pwr_planes.pdf+>). This > is > available online for free, so i m pasting it here. (I hope i can) > > In the following excerpt- > > "Suppose the transition is from low to high and the cross-section of > the > package has the transmission line located above a Vdd plane as shown > in > figure 1.The driver connects the Vdd plane to the transmission line > through > a low impedance.Current flows from the Vdd plane onto the > transmission line > which is low, say ground potential.As the wave front propagates down > the > transmission line, charge flows into the capacitance between the > trace and > the Vdd plane, raising the potential on the trace up to Vdd. The > current > path is complete because charge from the Vdd plane flows in a > complete loop > from the Vdd plane, through the driver and onto the transmission > line that > is referenced to the Vdd plane. If there is a ground plane > underneath the > Vdd plane, it is not disturbed because it is not part of the current > loop." > > Where does the return current flow? Does the return current flow > through the > inter-plane capacitance? Doesn't it need to flow thru a reference > plane? > > If it can't flow thru the Gnd plane, is it possible for it to flow > thru the > same power plane which is supplying the current (i hope not coz it > will > totally screw my fundamentals on current flow). > > 2)What if the package does not have an explicit power or ground > plane > i.e. Power > & Gnd are normal, thin traces (like other signal traces), > distributed > sporadically along with other I/Os, signal, clock traces etc. > (Although the > power & ground traces are de-coupled inside the chip & if the I/O > traces r > driven using a CMOS buffer) > > How is the return current going to flow now, when the I/O traces r > driven > using the buffer? > > Will the return current still look to flow through the nearest Power > or Gnd > reference trace it finds, given they are randomly routed in the > package like > ordinary traces? > > I'd really appreciate if somebody can clear this nagging doubt. > > Thanx in advance. > > Regards, > pras > > > ------------------------------------------------------------------ > To unsubscribe from si-list: > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject > field > > or to administer your membership from a web page, go to: > //www.freelists.org/webpage/si-list > > For help: > si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field > > > List technical documents are available at: > http://www.si-list.net > > List archives are viewable at: > //www.freelists.org/archives/si-list > or at our remote archives: > http://groups.yahoo.com/group/si-list/messages > Old (prior to June 6, 2001) list archives are viewable at: > http://www.qsl.net/wb6tpu > > > > ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu