[SI-LIST] Re: Return current of a trace in stripline
- From: "Loyer, Jeff" <jeff.loyer@xxxxxxxxx>
- To: "yousufs432@xxxxxxxxx" <yousufs432@xxxxxxxxx>
- Date: Mon, 5 Aug 2013 15:03:05 +0000
Hello Mustafa,
Can you share the details of your DDR failure? I would like to know the
specifics, since I have grown to have a different opinion on this issue, based
on my experience and studies.
From my experience and studies, I would expect Bala's primary concerns to be:
1) Noise from the power plane coupling onto the trace. If the power plane
is quiet and only 1V, there might not be any detrimental effect. A noisy 12V
plane, however, can induce a tremendous amount of noise on the signals.
2) Is there sufficient coupling between the various planes at transitions?
In my experience, this is usually not a problem. For realistic designs (clear
back to Front Side Bus days), I haven't been able to observe the impact of
changing reference planes. When there are reasonably thin dielectrics, several
planes, and the split between planes is narrow (5-10 mils), the transition
between planes of differing potentials can't be observed with TDR. But, this
is for server designs - perhaps a thick, low layer count board would behave
differently.
3) As I've said before, when crossing reasonably sized splits in planes, I
don't believe there's an issue with impedance discontinuities, crosstalk, or
EMI. In my posting of Dec. 13, 2012, I shared this experiment:
I had a test board with a long length (~13.5", or 343mm) of a microstrip
differential pair which I believe mimics an aggressor-victim pair.
a. I TDR'ed the traces single-endedly w/o modification as a "baseline",
observing the waveforms at the 4 ports as TDR, TDT, NEXT, and FEXT. As
expected for microstrip w/ lots of coupling, there was significant NEXT and
FEXT.
b. I then put a strip of copper tape over a portion of the microstrip
traces, to mimic a VDDQ plane adjacent to the signal traces which are
referenced to "GND". There was no DC connection between this copper shape and
"GND". The copper tape is very close to the traces (thickness of the
soldermask), probably quite a bit closer than the traces are to the "GND" plane
(dielectric thickness probably about 5 mils).
c. Again, I TDR'ed the traces single-endedly. As expected for stripline,
FEXT was dramatically reduced, NEXT was somewhat reduced for the portion under
the copper tape.
d. I then cut off a portion the copper tape with scissors - nothing very
precise.
e. This reduced the length of stripline portion, increasing FEXT, and
changing the time at which NEXT decreased.
f. I then replaced the portion of tape I had cut off, very close, but
probably not closer than our typical 5-10 mil gap between shapes, to that which
was still on the board. I checked that there was no DC continuity between the
two copper tape shapes. This mimicked (to my mind) a VDDQ plane split between
2 VDDQ shapes.
g. TDR'ing this and comparing it to that of a single plane showed:
i. The
difference in TDR was slight, and I attribute the difference to the slight
differences in how the tape was applied (it is not going to sit down as well
after being peeled off and reapplied)
ii. Similar
small differences in NEXT
iii. Very
slight, but measureable, differences in FEXT and Tp. While measureable, I
consider the difference in FEXT to be insignificant. I also don't know if the
trend would continue if I tried this many times.
iv. Perhaps
this would be grossly exacerbated by TDR'ing many signals simultaneously, but
I'm skeptical. When I tried to mimic that in the past for similar scenarios, I
have not been successful.
This indicated (to me) that crossing plane splits did not introduce significant
impedance discontinuity or crosstalk (or, I assume, EMI). Pictures of the
waveforms are available at
https://www.filesanywhere.com/fs/v.aspx?v6a6b8f61616e7aa0a2.
My experience indicates that, for designs I'm familiar with, noise coupling is
the primary worrisome agent when referencing signals to anything other than
ground. This might be different for 4-layer designs with less inter-plane
capacitance, but I don't think that referencing to something other than
"ground" is necessarily precluded.
I look forward to hearing of your specifics; perhaps it will shed some light on
exactly when it is a problem.
Thanks,
Jeff Loyer
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Mustafa Yousuf
Sent: Sunday, August 04, 2013 2:41 PM
To: bala89si@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Cc: yousufs432@xxxxxxxxx
Subject: [SI-LIST] Re: Return current of a trace in stripline
Hi Bala,
The return current is always split between the reference planes on both sides
of the trace. The farther the plane the less is the return current flowing in
that plane. From experience, in order for the return current to flow in the
closest reference plane, the other plane distance from the trace should in the
order 3-4 times as big as the distance of the closer plane.
In this case you have two issues:
1. both planes are almost at the same distance (3.7 and 4.3
mils) from the stripline, so the return current will be split almost equally
between the two.
2. The split in the power plane will cause serious problems.
The return current will look for the path of least inductance and you don't
know where that would be. It may very well hit a critical signal far away from
your original signal and result in significant cross talk to the other signal
which may be safe otherwise.
We had serious issues in similar situation (in DDR) as you described that
caused failure of the memory. Hence you should be concerned about this case.
Thanks,
Mustafa
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx<mailto:si-list-bounce@xxxxxxxxxxxxx>
[mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Balaji G
Sent: Sunday, August 04, 2013 11:43 AM
To: si-list@xxxxxxxxxxxxx<mailto:si-list@xxxxxxxxxxxxx>
Subject: [SI-LIST] Return current of a trace in stripline
Hi Experts,
We discussed a lot regarding path of return current before and this is
regarding the path of return current in a stripline trace. As far I learnt, the
return current will take the path of least resistance at low frequencies and
path of less inductance at high frequency and hence the reason that return
current travels in the plane directly under the signal's trace. My question is
if we consider a signal travelling in a stripline which is sandwiched between
the ground and split power plane where the signal to ground distance is 3.7mils
and signal to split power plane distance is 4.3mils, should we worry about the
split power plane at high frequency (say
3GHz) as the signal to ground distance is the path of least inductance and all
the return current for high frequency signal trace flows in the ground plane
causing no reflection/ EMI issues? Is my thinking right? Can you please
provide your thoughts on this?
Regards,
Balaji
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