[SI-LIST] Re: Return current of a trace in stripline
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: "Loyer, Jeff" <jeff.loyer@xxxxxxxxx>
- Date: Tue, 6 Aug 2013 12:15:33 -0400
For symmetric stripline, 1/2 half of the current will be referenced to the
split voltage plane. As a result, when comparing a microstrip split to
stripline with one of the two plane split, I would generally expect a 6 dB
reduction in crosstalk for the stripline case, given an apples-to-apples
comparison. That would mean 12 dB crosstalk peaking vs. the solid plane
baseline, compared to the 0 dB peaking that Mustafa and his team measured.
Yes, that is a 2 to 1 reduction, but there is still 5 to 1 effective
crosstalk peaking. This may, or many not, be a problem. However, if there
are large numbers of signals crossing the split, it only takes twice the
number switching simultaneously to make up the difference between
microstrip and stripline. Effectively this might push the probability of a
bit error further down the curve in a parallel single ended bus, since the
probability of multiple data bits aligning to form the worst case have been
reduced.
regards,
Scott
On Tue, Aug 6, 2013 at 11:04 AM, Loyer, Jeff <jeff.loyer@xxxxxxxxx> wrote:
> Thank you Mustafa for sharing that.
> For your case, it appears you were crossing a split in the plane of a
> microstrip structure, which is quite a different scenario than what I was
> addressing. I was addressing the original question of having a split in
> one of the reference planes of a stripline structure. I wish I knew your
> exact stackup; I believe that if you had a continuous plane on layer 3
> (assuming the microstrip is on layer 1 and the split plane is on layer 2)
> very close to layer 2, you would only have seen effects due to power plane
> noise.
> While I haven't tried your exact scenario, I have tried routing DDR data
> signals as microstrip referenced to VDDQ (as a pathological experiment).
> In that case, we found margin degradation was solely a function of noise
> on the VDDQ plane; we couldn't find any correlation to crosstalk
> aggressors. Note that, in this case, there wasn't any plane split, but
> there was a huge reference plane disconnect at the CPU and DIMMs.
>
> I'm not a big proponent of crossing split planes, but believe it shouldn't
> automatically be discarded lest you end up with more layers than you
> actually need.
>
> I am a proponent of understanding the mechanisms better so that we can
> intelligently decide when it's appropriate and when it's not.
>
> Thanks again for sharing your data and insights,
> Jeff Loyer
>
> From: Mustafa Yousuf [mailto:yousufs432@xxxxxxxxx]
> Sent: Monday, August 05, 2013 1:11 PM
> To: Loyer, Jeff
> Cc: bala89si@xxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: RE: [SI-LIST] Re: Return current of a trace in stripline
>
> Hello Jeff,
>
> Thanks for sharing you experience on this topic. I am not sure if we have
> ever personally met, but I know you from your good work via your
> presentations and emails inside and outside Intel.
>
> Part of our experience on this matter was from a detailed study we did at
> Intel to debug an actual SV board that failed the stress memory testing.
> This was published in DTTC and DesignCon:
>
> 1. Mustafa Yousuf, Brahim Bensalem, Naveid Rahmatullah, John
> Mcandrew, Srinivasan Rajagopalan., "Method to analyze cross talk between
> signals routed over split reference planes" August 3, 2008. Presented at
> DTTC, Intel Annual Conference, Intel Corporation. Internal Publication.
> 2. Mustafa Yousuf, Brahim Bensalem, Naveid Rahmatullah, John
> Mcandrew, Srinivasan Rajagopalan, "Analysis of cross talk between signals
> routed over discontinuous reference plane", Presented at DesignCon2009,
> February 2009.
>
> I like to note that we tried to capture the s-parameter model of the DDR
> site on our board using variable structure sizes on the board (different
> areas, different # of layers etc). Since the return current could stray out
> reaching to the closest return path to complete the least inductance loop,
> we were unable to observe the full strong effect until we included the
> entire DDR area with all layers included. This way the actual return path
> was captured and included in the s-parameter model. This (I mean modeling
> the entire structure surrounding the signal under study) is a key point
> that must be kept in mind since the signal under study is expected to
> interact with the entire structure.
>
> Thanks,
> Mustafa
>
> From: Loyer, Jeff [mailto:jeff.loyer@xxxxxxxxx]
> Sent: Monday, August 05, 2013 8:03 AM
> To: yousufs432@xxxxxxxxx<mailto:yousufs432@xxxxxxxxx>
> Cc: bala89si@xxxxxxxxx<mailto:bala89si@xxxxxxxxx>; si-list@xxxxxxxxxxxxx
> <mailto:si-list@xxxxxxxxxxxxx>
> Subject: RE: [SI-LIST] Re: Return current of a trace in stripline
>
>
> Hello Mustafa,
>
> Can you share the details of your DDR failure? I would like to know the
> specifics, since I have grown to have a different opinion on this issue,
> based on my experience and studies.
>
>
>
> From my experience and studies, I would expect Bala's primary concerns to
> be:
>
> 1) Noise from the power plane coupling onto the trace. If the power
> plane is quiet and only 1V, there might not be any detrimental effect. A
> noisy 12V plane, however, can induce a tremendous amount of noise on the
> signals.
>
> 2) Is there sufficient coupling between the various planes at
> transitions? In my experience, this is usually not a problem. For
> realistic designs (clear back to Front Side Bus days), I haven't been able
> to observe the impact of changing reference planes. When there are
> reasonably thin dielectrics, several planes, and the split between planes
> is narrow (5-10 mils), the transition between planes of differing
> potentials can't be observed with TDR. But, this is for server designs -
> perhaps a thick, low layer count board would behave differently.
>
> 3) As I've said before, when crossing reasonably sized splits in
> planes, I don't believe there's an issue with impedance discontinuities,
> crosstalk, or EMI. In my posting of Dec. 13, 2012, I shared this
> experiment:
> I had a test board with a long length (~13.5", or 343mm) of a microstrip
> differential pair which I believe mimics an aggressor-victim pair.
>
> a. I TDR'ed the traces single-endedly w/o modification as a
> "baseline", observing the waveforms at the 4 ports as TDR, TDT, NEXT, and
> FEXT. As expected for microstrip w/ lots of coupling, there was
> significant NEXT and FEXT.
>
> b. I then put a strip of copper tape over a portion of the microstrip
> traces, to mimic a VDDQ plane adjacent to the signal traces which are
> referenced to "GND". There was no DC connection between this copper shape
> and "GND". The copper tape is very close to the traces (thickness of the
> soldermask), probably quite a bit closer than the traces are to the "GND"
> plane (dielectric thickness probably about 5 mils).
>
> c. Again, I TDR'ed the traces single-endedly. As expected for
> stripline, FEXT was dramatically reduced, NEXT was somewhat reduced for the
> portion under the copper tape.
>
> d. I then cut off a portion the copper tape with scissors - nothing
> very precise.
>
> e. This reduced the length of stripline portion, increasing FEXT, and
> changing the time at which NEXT decreased.
>
> f. I then replaced the portion of tape I had cut off, very close,
> but probably not closer than our typical 5-10 mil gap between shapes, to
> that which was still on the board. I checked that there was no DC
> continuity between the two copper tape shapes. This mimicked (to my mind)
> a VDDQ plane split between 2 VDDQ shapes.
>
> g. TDR'ing this and comparing it to that of a single plane showed:
>
> i. The
> difference in TDR was slight, and I attribute the difference to the slight
> differences in how the tape was applied (it is not going to sit down as
> well after being peeled off and reapplied)
>
> ii.
> Similar small differences in NEXT
>
> iii. Very
> slight, but measureable, differences in FEXT and Tp. While measureable, I
> consider the difference in FEXT to be insignificant. I also don't know if
> the trend would continue if I tried this many times.
>
> iv.
> Perhaps this would be grossly exacerbated by TDR'ing many signals
> simultaneously, but I'm skeptical. When I tried to mimic that in the past
> for similar scenarios, I have not been successful.
>
> This indicated (to me) that crossing plane splits did not introduce
> significant impedance discontinuity or crosstalk (or, I assume, EMI).
> Pictures of the waveforms are available at
> https://www.filesanywhere.com/fs/v.aspx?v�b8f61616e7aa0a2.
>
>
>
> My experience indicates that, for designs I'm familiar with, noise
> coupling is the primary worrisome agent when referencing signals to
> anything other than ground. This might be different for 4-layer designs
> with less inter-plane capacitance, but I don't think that referencing to
> something other than "ground" is necessarily precluded.
>
>
>
> I look forward to hearing of your specifics; perhaps it will shed some
> light on exactly when it is a problem.
>
>
>
> Thanks,
>
> Jeff Loyer
>
>
>
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx<mailto:si-list-bounce@xxxxxxxxxxxxx>
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Mustafa Yousuf
> Sent: Sunday, August 04, 2013 2:41 PM
> To: bala89si@xxxxxxxxx<mailto:bala89si@xxxxxxxxx>; si-list@xxxxxxxxxxxxx
> <mailto:si-list@xxxxxxxxxxxxx>
> Cc: yousufs432@xxxxxxxxx<mailto:yousufs432@xxxxxxxxx>
> Subject: [SI-LIST] Re: Return current of a trace in stripline
>
>
>
> Hi Bala,
>
>
>
> The return current is always split between the reference planes on both
> sides of the trace. The farther the plane the less is the return current
> flowing in that plane. From experience, in order for the return current to
> flow in the closest reference plane, the other plane distance from the
> trace should in the order 3-4 times as big as the distance of the closer
> plane.
>
> In this case you have two issues:
>
> 1. both planes are almost at the same distance (3.7 and
> 4.3 mils) from the stripline, so the return current will be split almost
> equally between the two.
>
> 2. The split in the power plane will cause serious
> problems. The return current will look for the path of least inductance and
> you don't know where that would be. It may very well hit a critical signal
> far away from your original signal and result in significant cross talk to
> the other signal which may be safe otherwise.
>
> We had serious issues in similar situation (in DDR) as you described that
> caused failure of the memory. Hence you should be concerned about this case.
>
>
>
> Thanks,
>
>
>
> Mustafa
>
>
>
>
>
>
>
> -----Original Message-----
>
> From: si-list-bounce@xxxxxxxxxxxxx<mailto:si-list-bounce@xxxxxxxxxxxxx>
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Balaji G
>
> Sent: Sunday, August 04, 2013 11:43 AM
>
> To: si-list@xxxxxxxxxxxxx<mailto:si-list@xxxxxxxxxxxxx>
>
> Subject: [SI-LIST] Return current of a trace in stripline
>
>
>
> Hi Experts,
>
> We discussed a lot regarding path of return current before and this is
> regarding the path of return current in a stripline trace. As far I learnt,
> the return current will take the path of least resistance at low
> frequencies and path of less inductance at high frequency and hence the
> reason that return current travels in the plane directly under the signal's
> trace. My question is if we consider a signal travelling in a stripline
> which is sandwiched between the ground and split power plane where the
> signal to ground distance is 3.7mils and signal to split power plane
> distance is 4.3mils, should we worry about the split power plane at high
> frequency (say
>
> 3GHz) as the signal to ground distance is the path of least inductance and
> all the return current for high frequency signal trace flows in the ground
> plane causing no reflection/ EMI issues? Is my thinking right? Can you
> please provide your thoughts on this?
>
>
>
> Regards,
>
>
>
> Balaji
>
>
>
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--
Scott McMorrow
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