[SI-LIST] Resend: the upper frequency of power integrity simulation

  • From: Tesla <emcesd@xxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Fri, 9 Mar 2012 14:47:39 +0800 (CST)




Hi,
 
I read documents about power integrity simulation.
Most of documents said "keep the impedance 1mohm from DC to XXX MHz "
How to decide the upper frequency in simulation.
Is it related to the I/O running frequency?  eg, My FPGA run at 200MHz. So i 
set the upper frequency as 200X5=1GHz. Am i right?
 
Thanks
 
Tesla




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