Hi all, Decoupling for BGA is a important topic, especially for the core power net in which there are so many capacitors. Because the location of decoupling capacitors are required as possible as close to the device in the IC's datasheet , what's more, there are very little areas for placement. There are tow way for this question, one hand is using smaller package, such as 0402,0201; the other hand is place cap around IC; As my experence,the first method is more easier, usually, take sure that one cap per tow or three pins.but for the second method, it is difficult for the larger loop inductance. but I think it is very imposible, its essence is how large the cap's parasitic inductance is. As long as the loop inductance is enough small, the method is feasible.How to calculate the loop inductance? exept for simulation soft, can we get a simple formula to evaluate it? ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu