[SI-LIST] Regarding the air gap between via hole and copper

  • From: "Pang Ning" <pangning2000@xxxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Fri, 15 Jul 2005 15:31:13 +0800

Dear Experts,

I have a simple question about the gap between the via hole pad and 
surrounding copper. In VCC layer, I used positive plane. Because the board 
size is small, in order to give wider spacing for power between via holes, I 
used 5mil air gap between via pad and the copper. I don't know whether this 
spacing(5mil) will cause some problems such as crosstalk from via holes, low 
yield issue... Is 5mil too small for the gap? Could you give me some 
suggestions if you think there is anything wrong?


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