Yes, as per datasheet. But it is not driving DQS_N during READ.
On 29 June 2016 at 16:06, Brijesh Shah <Brijesh.Shah@xxxxxxxxxxx> wrote:
Hi Malli,
If the model is configured for DDR2 differential, NAND should drive DQS_N
as well.
Thanks,
Brijesh
*From:* Malli K [mailto:malli.1729@xxxxxxxxx]
*Sent:* Tuesday, June 28, 2016 8:38 PM
*To:* Brijesh Shah <Brijesh.Shah@xxxxxxxxxxx>
*Cc:* si-list@xxxxxxxxxxxxx
*Subject:* Re: [SI-LIST] Re: Regarding NAND Flash DQS signal amplitude
difference during Read & Write
Hi Brijesh,
For WRITE operation, DQS_P & N are toggling properly. Only For READ
operation DQS_N stays at VREF level.
IT is configured for DDR2 mode with Differential DQS signalling. Why you
mentioned it's not configured for DDR2 mode. we are using nv-DDR2 Mode 6
On 28 June 2016 at 17:51, Brijesh Shah <Brijesh.Shah@xxxxxxxxxxx> wrote:
Hi,
Looks like NAND model is not configured in differential mode. For DDR2, it
should be differential.
Thanks,
Brijesh
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Malli K
Sent: Tuesday, June 28, 2016 4:46 PM
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Regarding NAND Flash DQS signal amplitude
difference during Read & Write
Hi,
We are seeing during READ operation DQS_N is not toggling during data
transfer. It stays VREF level. Only DQS_P is toggling.
For WRITE operation, both DQS_P and N are toggling in 180 degC.
That's why we are seeing DQS_Differential amplitude is less in READ than
WRITE operation.
I am not sure why this is the case. NAND vendor should answer i guess.
DQS is configured as differential.
On 22 April 2016 at 16:25, Mallikarjun K <malli.1729@xxxxxxxxx> wrote:
Hi Adrien,the amplitude.
I don't have any test points for DQ & DQS near controller. I will
check if i can tap any via.
On 22 April 2016 at 13:55, Adrien Augé <auge.adrien@xxxxxxxxx> wrote:
Hi
I can see two things:
ISI - controller may have higher output slew rate thus higher
amplitude on the DQS while the lower output slew from NAND might limit
Probing point. - "We are capturing signals near to NAND Flash always."
-> This will bring reflection (should probe as close as possible to
-> the
wrote:receiver -> controller)
Regards
Adrien
On Apr 21, 2016, at 12:03 PM, ê¶ê¸°ì <keeyoung.kwon@xxxxxxxxxxxxxx>
I suspect that the current path on NAND side as belwo.
I misunderstood you were using 667Mbps.
Besides, if you were talking about some measured waveforms for
333Mbp,
density, the high frequency Tx current of NAND flash can be little
Compared to Program case, if NAND flash has multiple dies to
increase
smaller than that of NAND host device because of the
frequency-dependent current path caused by "N x Cio".
On Behalf Of ê¶ê¸°ì
Regards,
Keeyoung
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
Sent: Thursday, April 21, 2016 11:41 AMdifference during Read & Write
To: malli.1729@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Regarding NAND Flash DQS signal amplitude
for overdrive2(18 Ohm), but it is little slow for 667Mbps NV-DDR2.
Hi,
I suspect there are ISI and overclocking issue in the IBIS model.
I would recommend to check output slew rate of NAND Tx buffer.
According to ONFI 4.0 spec., the minimum output slew rate is
1.0V/nsec
On Behalf Of Mallikarjun K
I think it should be at least more than 2 V/nsec for 667Mbps.
I hope this helps...
Regards,
Keeyoung
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
Sent: Tuesday, April 19, 2016 4:40 PMduring Read & Write
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Regarding NAND Flash DQS signal amplitude
difference
of 333MT/s (Clock frequency :166Mhz).
Hi,
We are using NAND flash in nv-DDR2 mode. Operating at maximum data
rate
differential signal amplitude is *less than* when WRITE operation.
During Our DVT, we found that During Read Operation the DQS
WRITE operation pk-pk ~ 3.8V
READ operation pk-pk ~ 3.2V (that too negative side swing is less)
Signal quality is good in both cases.
We are capturing signals near to NAND Flash always.
Any thoughts on this.,
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