[SI-LIST] Re: Regarding NAND Flash DQS signal amplitude difference during Read & Write

  • From: 권기영 <keeyoung.kwon@xxxxxxxxxxxxxx>
  • To: "malli.1729@xxxxxxxxx" <malli.1729@xxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 21 Apr 2016 02:41:26 +0000

Hi,
I suspect there are ISI and overclocking issue in the IBIS model.
I would recommend to check output slew rate of NAND Tx buffer.

According to ONFI 4.0 spec., the minimum output slew rate is 1.0V/nsec for 
overdrive2(18 Ohm), but it is little slow for 667Mbps NV-DDR2.

I think it should be at least more than 2 V/nsec for 667Mbps.

I hope this helps...

Regards,
Keeyoung


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Mallikarjun K
Sent: Tuesday, April 19, 2016 4:40 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Regarding NAND Flash DQS signal amplitude difference during 
Read & Write

Hi,
We are using NAND flash in nv-DDR2 mode. Operating at maximum data rate of 
333MT/s (Clock frequency :166Mhz).

During Our DVT, we found that During Read Operation the DQS differential signal 
amplitude is *less than* when WRITE operation.

WRITE operation pk-pk  ~ 3.8V
READ operation pk-pk ~ 3.2V (that too negative side swing is less)

Signal quality is good in both cases.

We are capturing signals near to NAND Flash always.

Any thoughts on this.,


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