[SI-LIST] Reg: Default state of FPGA GPIOs at power on

From: "Marimuthu P." <marimuthu_p@xxxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Date: Thu, 20 Sep 2007 14:55:29 +0530

Hi All,
 

In one of our FPGA development board we have one CPU from which SRAM_CSn is
going to SRAM, CPLD and to one connector. When CPU is the master it will
access the SRAM and code is running fine. We wanted to test FPGA as the
master, but we don't have any physical connection of SRAM_CSn from FPGA to
SRAM. Other signals are fine and we are using nXBREQ and nXBACK of CPU to get
the bus control for MAC. So to make the connection of SRAM_CSn to FPGA, we
externally connected one wire from FPGA I/O pin to SRAM_CSn. But with this
connection if I power on the board without loading any image into FPGA, the
CPU to SRAM access stops. If I probe the signal its high (3.3V). If you have
any idea of why this is happening and what is the solution to solve this
problem, please share with me.

 

With regards,

Marimuthu P

 

 



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[SI-LIST] Reg: Default state of FPGA GPIOs at power on

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