[SI-LIST] Re: Reducing Reflections in packages
- From: "Grasso, Charles" <Charles.Grasso@xxxxxxxxxxxx>
- To: "'scott@xxxxxxxxxxxxx'" <scott@xxxxxxxxxxxxx>,"'wesley_wu@xxxxxxxxxxx'" <wesley_wu@xxxxxxxxxxx>,'silist' <si-list@xxxxxxxxxxxxx>
- Date: Tue, 13 Jan 2004 07:42:14 -0700
Wesley - Without giving away company secrets, can you tell us
what the I/O is and what frequency the I/O and the chip is
running at?
Best Regards
Charles Grasso
Senior Compliance Engineer
Echostar Communications Corp.
Tel: 303-706-5467
Fax: 303-799-6222
Cell: 303-204-2974
Email: charles.grasso@xxxxxxxxxxxx;
Email Alternate: chasgrasso@xxxxxxxx
-----Original Message-----
From: Scott McMorrow [mailto:scott@xxxxxxxxxxxxx]
Sent: Monday, January 12, 2004 5:49 PM
To: wesley_wu@xxxxxxxxxxx; silist
Subject: [SI-LIST] Re: Reducing Reflections in packages
Wesley,
The range of options depends upon the BGA technology you are using. Are
you using ceramic, organic or PTFE laminates? Any optimizations will
depend upon the laminate material properties, since the Er of the
laminate determines the capacitance of vias, traces and pads. Ceramic
substrates can be a pain to optimize due to the high Er, whereas PTFE
substrates are quite a bit easier.
For good ball transitions on organic/plastic packages, a 1.27 mm pitch
is desired. Anything smaller than this will cause increased return
loss, due to the low impedance of the via/ball/pad structures.
On the bump side of the package, it is your silicon capacitance that
dominates. There is not much you can do in the package to alleviate
this, except to reduce the capacitance of the trace and increase it's
inductance as it approaches the bump to compensate for the increased die
capacitance. Alternately, there are some silicon design techniques that
can be used to compensate for input capacitance.
Other tricks:
* increase trace to ball transition via spacing
* place antipads underneath ball pads to reduce capacitance.
* use differential signalling to allow for better return path control
* use a 1.27 mm ball pitch to achieve a closer to 50 ohm SE and 100
ohm differential via/ball/pad impedance.
* provide plane relief holes underneath PCB ball pads.
* use large oval antipads around differntial vias and balls
* design both the package and PCB with as wide a trace as possible
by increasing laminate thickness. This will reduce the
capacitance differential between the traces and pads and reduce
the impedance mismatch.
* add inductive elements in the design to provide peaking in the
high frequency response.
* add high frequency capacitance compensation elements into the
design on the die.
* if you are using inputs with termination, design capacitive
compensation into the termination circuitry.
regards,
scott
--
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com
wesley_wu@xxxxxxxxxxx wrote:
>Dear Experts,
>
>Recently we have had experiences with excessive
>reflections with BGA packages. The two interfaces,
>solder ball side and bump side, exhibit substantial
>impedance value drops as evidenced on TDR as
>capacitive dips. There are a few ways I can think of
>to raise the inductance of the balls and bumps, and at
>the same time lower the capacitance, e.g. smaller land
>diameters, longer bumps and balls, bigger antipads,
>etc. But in such tight spaces I don't know how
>practical they are. Would anyone like to share
>experiences in dealing with similar situations? Thanks
>so much in advance.
>
>ww
>
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