Hi Doug,
yes, we agree. In fact I never disagreed (sorry if it sounded like
disagreement). I just wanted to stress the fact that there are cases where via
heating does make a difference. The Article headline sounded like "Please don’t
ever think about via heating at all, it is just not there!!!" This would be
just bad engineering because every rule has its limits, and designers need to
know the limits (or need to know that they MIGHT never reach this limit but
have to keep in mind that there in fact is one).
When you say:
" But that leads to another conclusion in the book. You are correct that there
is an influence from other traces and other components. In fact, the entire
problem is so complicated that it cannot be solved by a set of charts or a set
of equations.", then I think that’s exactly what I was missing in the article:
a conclusion that a single heat source can't be viewed individually as each
heat source plays a role in the big picture.
BR
Gert
----------------------------------------
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& Co. KG; Generalbevollmächtigte Gesellschafterin: Dipl.-Hdl. Margrit Harting
-----Original Message-----
From: Doug Brooks [mailto:dbrooks9@xxxxxxxxxxxxxxx]
Sent: Friday, March 18, 2016 3:42 PM
To: Havermann, Gert; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: Recommendations on Current Carrying Capacity of Vias
on PCB's - clarification
I think we mostly agree in general, but not in degree of effect..
For example, assume you have a single via for a trace. It will have a
temperature (which will be similar to the trace, depending on
specifics.) Now if you have multiple vias (same trace) carrying same total
current (which the trace presumably can handle) the vias will share the current
and be (individually) cooler. If you have multiple vias, each independent and
carrying heavy current, then by definition you have multiple traces, too. True,
there may be a concentration of heat around the vias, but there will also be a
concentration of heat around the traces. (This is covered in another chapter in
my book.) So, back to the statement, if the traces are designed properly to
carry the heat and load, then the empirical results suggest a single via is all
that is necessary. It is the thermal conductivity between the via and the trace
that dominates all else regarding the via temperature.
But that leads to another conclusion in the book. You are correct that there is
an influence from other traces and other components. In fact, the entire
problem is so complicated that it cannot be solved by a set of charts or a set
of equations. We are headed to the point where we will need computer
simulations (using programs like Johannes Adam's TRM simulation program) to
solve them. And there is a precedent for this. 20 years ago, we could solve the
controlled-impedance problem using the equations contained in IPC publications.
But today we know we need field effect solutions. We are headed the same
direction in trace thermal issues.
Doug
Havermann, Gert wrote:
Hi Doug,
thanks for the clarification, I thought it was a 3D view with transparent
Board Material.
Some further comments:
"First, it is not the air that cools the trace, it is the board material."
That’s true, and essential to co-heating. Heat travels away from the
generator towards cooler places taking the way of least thermal resistance.
Air has a higher resistance than FR4 or Copper, thus most of the heat will
travel on copper, then FR4. But in the end it has to be radiated to air as
the PCB isn't isothermal (if it was it would heat up until it reaches a
constant temperature all over the PCB).
In all cases where the via is the heat generator (the current bottleneck)
problems can begin. If you place "heat generating Vias" close together, the
heat generated by them will not travel from Via to Via (because their
temperature is equal), thus it can only travel in the opposite direction.
This results in a rise of thermal resistance (due to reduced
heat-travel-path) resulting in a higher temperature difference between Vias
and surrounding material (copper trace). This needs to be taken into account
for higher currents and denser Designs. And remember that many components
generate heat too, and they also use the traces as heatsink.
"the via will be the same temperature (or slightly hotter than) the parent
trace, whatever that temperature is." That’s true, the main problem is that
when the via itself starts to generate more heat than the trace, then it can
become critical under certain circumstances. For High Power applications the
Designer should be aware of that and Design vias (and via patterns) that will
not gerenate more heat than the trace it is connected to.
BR
Gert
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Absender ist HARTING KGaA; Marienwerderstraße 3, D-32339 Espelkamp;
Registergericht: Bad Oeynhausen; Register-Nr.: HRB 8809; Vorsitzender
des Aufsichtsrats: Dipl.-Kfm. Jörg Selchow; persönlich haftende
Gesellschafter: Dipl.-Kfm. Dr.-Ing. E.h. Dietmar Harting, Philip F.W.
Harting, Maresa Harting-Hertz; HARTING WiMa AG (Luxemburg) & Co. KG,
HARTING Beteiligungs GmbH & Co. KG; Generalbevollmächtigte
Gesellschafterin: Dipl.-Hdl. Margrit Harting
-----Original Message-----
From: Doug Brooks [mailto:dbrooks9@xxxxxxxxxxxxxxx]
Sent: Thursday, March 17, 2016 5:34 PM
To: Havermann, Gert; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: Recommendations on Current Carrying
Capacity of Vias on PCB's - clarification
Let me clarify response 1.
I don't report in the article that the bottom trace is cooler than the top
trace. This is true (for the reason stated) but the difference is not too
great. What you may be referring to is what appears on the right hand side of
Figures 2 and 3. Perhaps it is not clear that the figures represent the
thermal profile of the top layer(only), not the complete trace. The trace
continues on through the via to the bottom layer, which looks very much like
the top layer thermal layer, but flipped horizontally.
Thanks for the comments. Here are a couple of responses.
1. Actually, the bottom trace is thicker than the top trace (see note 2 in
the article.) This was caused by the normal plating tolerances in the board
fabrication process. That is why it is cooler.
2. Co-heating is complicated. My first article in the magazine (repeated on
the UltraCAD website as "Trace Currents and Temperatures, Revisited") goes
into this in some detail. But here are two considerations of note:
First, it is not the air that cools the trace, it is the board material.
That is why the internal traces run cooler than the external ones do
(the most revolutionary results of IPC 2152). Second, co-heating tends
to transfer heat from the generator (the trace carrying the current)
to the adjacent trace/plane. Hence the generator runs cooler. But
regardless, the via will be the same temperature (or slightly hotter
than) the parent trace, whatever that temperature is.
My new book (end of April) will go into all of this (and LOTS more).
Watch for the announcement on www.ultracad.com
Doug
Havermann, Gert wrote:
Hello Doug,------------------------------------------------------------------
nice report, but I have some questions and some remarks.
First the questions:
-Why is the bottom trace cooler than the Top trace? (must be some
boundary setting as the traces are the same size, right?) -Which Thermal
boundary has been used?
Remarks:
I think the conclusions aren't precisely pronounced and can be
misunderstood. Your test showed that the 10 mil via is not the
thermal bottleneck when the trace is wide enough for the current.
This is purely based on a test vehicle without Co-heating and with
traces running on outer Layers. In these (rare) cases, the trace will
act as a heatsink, cooling away the heat created by the via. But
still the via creates heat, and in more dense designs and higher
currents the heat is not transferred to the air, and you will see
higher temperature rises at vias as each via will heat up the
surrounding vias and traces (called Co-heating). The conclusion that
no via can be small enough to burn up (that’s what it sounds when you
state: the current will not heat up a via)
The same behavior is seen in connectors, where the tiny contact point is
cooled by the Mass of the contact and the Copper cable and traces attached
to the contact. But as soon as you add mode contacts into a tiny housing,
the cooling effect drops dramatically. Many designers don't take co-heating
into account, and then the connectors burn away due to overheating even
though each single contact was derated to carry a the amount of current that
was applied to it, but the derating was done for individual contacts.
BR
Gert
----------------------------------------
Absender ist HARTING KGaA; Marienwerderstraße 3, D-32339 Espelkamp;
Registergericht: Bad Oeynhausen; Register-Nr.: HRB 8809; Vorsitzender
des Aufsichtsrats: Dipl.-Kfm. Jörg Selchow; persönlich haftende
Gesellschafter: Dipl.-Kfm. Dr.-Ing. E.h. Dietmar Harting, Philip F.W.
Harting, Maresa Harting-Hertz; HARTING WiMa AG (Luxemburg) & Co. KG,
HARTING Beteiligungs GmbH & Co. KG; Generalbevollmächtigte
Gesellschafterin: Dipl.-Hdl. Margrit Harting
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Doug Brooks
Sent: Thursday, March 17, 2016 3:14 PM
To: lekannat@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Recommendations on Current Carrying Capacity
of Vias on PCB's
Very timely question.
Check out the article that appeared in the Feb issue of PCD&F "Empirical
Confirmation of Via Temperatures." Here is a link:
http://www.pcdandf.com/pcdesign/index.php/magazine/10604-thermal-mode
l
ing-1602
The answer is that via temperature is NOT determined by via current. The
reason is that the thermal coupling s so good between the trace and the via
that as long as the trace is sized correctly, the via cannot overheat.
Therefore, only a single small via is required.
I will be speaking to the local Designer's Council (Seattle) tentatively
scheduled for May 4th. Also watch for a new book on this topic to be
published and available on Amazon by the end of April.
Leojik Kannathara wrote:
Hi Experts,------------------------------------------------------------------
I am working on PowerDC simulation of PCB's and would like to understand if
there is a general guidance on the current carrying capacity of vias. I
have been going through IPC 2152 to understand if I can correlate via sizes
to current carrying capacity, but I am not able to make a clear correlation.
Are there rules of thumbs or a via size to current (in Amps) correlation /
specific literature in this area that people in the industry could point me
too ?
Are there differentiation on current carrying capacity based on different
types of visa - buried, through, micro vias ?
Regards,
Leojik Kannathara
Signal Integrity Engineer
Microsoft
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