[SI-LIST] Re: 回复： Re: trace impedance difference in same signal group of Intel guide
- From: Hermann Ruckerbauer <hermann.ruckerbauer@xxxxxxxxxxxxx>
- To: Heyfitch <heyfitch@xxxxxxxx>
- Date: Fri, 07 May 2010 07:27:41 +0200
Hello,
another possible explanation:
What did they assume for the Spacing ?
if they use the 28 OHm on a Microstrip line they do get a quite wide
line. Assuming the same pitch, this will result in less spacing which
might be critical on a Microstrip line, but no problem on a stripline.
So overall there are several reasons mentioned why this could make
sense. Maybe Intel had some of this reasons, or it was just decided
based on simulation optimization ... You can never know ...
Hermann
EKH - EyeKnowHow
Hermann Ruckerbauer
www.EyeKnowHow.de
Hermann.Ruckerbauer@xxxxxxxxxxxxx
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94554 Moos
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schrieb Heyfitch:
> This is just a hypothesis...
> They allocated a fixed timing budget for the skews due to crosstalk - the
> same number of picoseconds irrespective of the microstrip or stripline,
> short or long trace. Therefore, the td/inch variation has to be controlled
> tighter for the B-bus, the longer of the two buses. The delta between the
> even and odd mode impedances becomes lower as the single line Z0 gets
> lower. The same is probably true for the difference between the even and
> odd mode velocity delta. I suggest you experiment with a set of three
> coupled lines in a 2D field solver to verify this.
> - Vadim
> On Thu, May 6, 2010 at 8:28 PM, fei xue <harrison_cls@xxxxxxxxxxxx> wrote:
>
>
>> Hello Jon Powell,
>> Yes, channel A is expected to be routed on top and bottom layers with trace
>> impedance 37Ohm+/-15%, channel B is expected to be routed on internal signal
>> layers with trace impedance 28Ohm+/-10% from Intel MCH3210 PDG document.
>>
>> Is this the reason why Intel expects different trace impedance on different
>> channel with different layers? why? Could anybody give reasonable explain on
>> this together with my below 4 questions. Thanks!
>>
>> Harrison
>>
>>
>>
>> ________________________________
>> å��件人ïÅ?� "Powell, Jon N" <jon.n.powell@xxxxxxxxx>
>> æ�¶ä»¶äººïÅ?� Aubrey Sparkman
>> <asparky@xxxxxxxxxxxxxxxxxxxxxxxx>; "Grasso, Charles"
>> <Charles.Grasso@xxxxxxxxxxxx>; fei xue <harrison_cls@xxxxxxxxxxxx>; "
>> si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
>> å��é��æ�¥æ��ïÅ?� 2010/5/7 (��) 12:05:20
>> ��
>> äž» é¢�ïÅ?� [SI-LIST] Re: trace impedance difference in same
>> signal group of Intel
>> guide
>>
>> Are these channels expected to be routed on different layers?
>>
>> Like is CHA on Microstrip and CHB on Stripline?
>>
>> Jon Powell
>>
>> EPSD Product SI
>>
>> DISCLAIMER:
>> Though I work for Intel, I am not a spokesperson for Intel nor is this an
>> official communication.
>> The opinions stated are my own and not necessarily that of Intel.
>>
>>
>> $BUr(B
>>
>>
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>> On Behalf Of Aubrey Sparkman
>> Sent: Thursday, May 06, 2010 7:48 AM
>> To: 'Grasso, Charles'; 'fei xue'; si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] Re: trace impedance difference in same signal group of
>> Intel guide
>>
>> Harrison,
>>
>> IF your company is large enough to be supported by Intel, you must ask
>> yourself whether you value their support. If you do, you will follow their
>> guidelines. If not, you are free to develop your own guidelines.
>>
>> Aubrey Sparkman
>> 512-461-6165
>> asparky@xxxxxxxxxxxxxxxxxxxxxxxx
>>
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>> On
>> Behalf Of Grasso, Charles
>> Sent: Thursday, May 06, 2010 8:26 AM
>> To: fei xue; si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] Re: trace impedance difference in same signal group of
>> Intel guide
>>
>> I'd ask Intel. Looking at the numbers theres not a whole lot of difference
>> between a 37ohm -15% trace and a 28ohm +10% trace. These specs look a
>> little strange! Anyone from Intel on the line??
>>
>>
>> ________________________________________
>> From: si-list-bounce@xxxxxxxxxxxxx [si-list-bounce@xxxxxxxxxxxxx] On
>> Behalf
>> Of fei xue [harrison_cls@xxxxxxxxxxxx]
>> Sent: Wednesday, May 05, 2010 1:12 AM
>> To: si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] trace impedance difference in same signal group of Intel
>> guide
>>
>> Hello all,
>> May I raise a question to all of you, as you know, Intel does more
>> constraints restrictions than any other semiconductor vendor especially in
>> MCH platform design guide (PDG). For example, in DDR2 control group signal
>> constraints (CKE, CS and ODT signals) of Intel Bigby 3210 MCH chipset, the
>> characteristic trace impedance of the DDR2 control group signals from MCH
>> to
>> Channel A dimms is 37Ohm+/-15%, however the characteristic trace impedance
>> from MCH to Channel B dimms is 28Ohm+/-10%. The traces of Channel B dimms
>> are longer than Channel A dimms. My question are,
>>
>> 1, why is the trace characteristic trace impedance of Channel A dimms
>> different from impedance of Channel B dimms.
>> 2, I checked the IBIS model, the output buffer model of Channel A dimms is
>> the same as model of Channel B dimms, they are 38.9Ohm (I got this from
>> IBIS
>> VI curves), so it is not the reason of buffer output impedance.
>> 3, I do not think the trace impedance's difference is because of trace
>> distance difference between Channnel A and Channel B, 37Ohm and 28Ohm are
>> big gaps.
>> 4, PCB manufactory gave us feedback that they can not control trace
>> impedance within 28Ohm+/-10%, what they can do is controlling impedance
>> within 28Ohm+/-5Ohm, how to evaluate this impact? can we confirm with
>> manufactory that controlling impedance within 28Ohm+/-5Ohm is ok or not.
>>
>> I appreciate if you have any hints on this.
>>
>> Harrison
>>
>>
>>
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