[SI-LIST] 答复: Re: placement of decouplingcaps (again)
- From: yu.yanfeng@xxxxxxxxxx
- To: zhang_kun@xxxxxxxxxx
- Date: Fri, 16 Apr 2004 13:44:20 +0800
One correction.
"The final is at the power ground pin of Die." should be "Power/Gnd grid
on the Die", not power/ground pin.
Yanfeng Yu
Sr. Engineer
Nanjing R/D center, ZTE Corp.
63 Gongqingtuan Road, Nanjing 210012
Phone: 86-25-52872410
Mobile :13505159475
Mail: yu.yanfeng@xxxxxxxxxx
zhangkun 29902 <zhang_kun@xxxxxxxxxx>
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2004-04-16 13:16
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Ö÷Ì⣺ [SI-LIST] Re: placement of decoupling caps (again)
Dear all
There are a lot of good discussion on the placement of decoupling
capacitors. I agree with Raymond that the "rule of experts" is not always
right. When and where will affect the result. For ADSL, the decoupling
below 3MHz is critical. For SDRAM of 50MHz, the decoupling from 10MHz to
400MHz is critical.
In power integrity, there are several stage.
VRM=>PCB=>Package=>Die.
The final is at the power ground pin of Die. At PCB level, it could not be
completely solved. Whether the decoupling is good or bad should be decided
by the impedance at the power ground pin of Die and the noise source of
Die.
Therefore, I think it is of no use to discuss which is better or not
without the details of the product.
My recommandation is that "Do simulation and check the impedance".
Best Regards
Zhangkun
2004.4.16
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