It is better to continue the discussions once the data is out, towards
the end of January.
It is going to be PCIe Gen3.
Regards,
Istvan Novak
Oracle
On 11/4/2015 8:10 PM, yu.yanfeng@xxxxxxxxxx wrote:
Yes, It depends on the work frequency.
But I fully agree with Lee's opinion. It's nothing, just a waste of
engineering time and pcb estate, if you try to do simulation and add
those stiching via in normal
PCIe Gen3 designs.
yanfeng
*Istvan Novak <istvan.novak@xxxxxxxxxxx>*
å件人: si-list-bounce@xxxxxxxxxxxxx
2015/11/05 08:59
请çå¤ ç»
istvan.novak@xxxxxxxxxxx
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leeritchey@xxxxxxxxxxxxx, dmarc-noreply@xxxxxxxxxxxxx,
si-list@xxxxxxxxxxxxx,
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bbakshan@xxxxxxxxx, Kevin.Hou@xxxxxxxxxx
主é¢
[SI-LIST] Re: What's the purpose of stitching vias which just connect
one GND layer?
Lee,
As always, it depends. One of the presentations our team is going to do
at DesignCon 2016 will describe (with data) a scenario when stitching
vias are needed.
Regarding the original post though, if a stitching via is attached only
to one plane layer close to the surface (ground or power) it is prone to
quarter-wave resonance, which carries its own risks.
Regards,
Istvan Novak
Oracle
On 11/4/2015 7:51 PM, Lee Ritchey wrote:
Much speculation in this message! Where is the proof?many very
There are millions of PCBs shipped every month with who knows how
high speed transmission lines without stitching vias. In fact, theproducts
would be unroutable if stitching vias were required.[mailto:si-list-bounce@xxxxxxxxxxxxx] On
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
Behalf Of heyfitch (Redacted sender "heyfitch" for DMARC)localized -
Sent: Wednesday, November 4, 2015 11:53 AM
To: si-list@xxxxxxxxxxxxx
Cc: leeritchey@xxxxxxxxxxxxx; bbakshan@xxxxxxxxx; Kevin.Hou@xxxxxxxxxx
Subject: [SI-LIST] Re: What's the purpose of stitching vias which just
connect one GND layer?
Had there been no stitching via, simulations would not have been
just as the physical reality would not be localised. That is both thetype...), and
simulation results would be sensitive to the BC (proximity,
the diff vias (e.g.) would couple thru planes and plane edges.attachment.Transmission
Worse, simulations would not be predictive of the physical reality.
For CBCPW, you stitch to extinguish higher propagation modes, thus
preventing energy leaking into them from the diff and common modes.
Regards,
Vadim Heyfitch
Sent from my phone
On Nov 3, 2015, at 12:07, Boris Bakshan <bbakshan@xxxxxxxxx> wrote:
Best answer so far on the SI-list ! :)
On Tue, Nov 3, 2015 at 9:51 PM, Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
wrote:
Those stitching vias keep the CAD department busy and raise the cost
of the PCB. Not much else.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
On
Behalf Of Kevin Hou
Sent: Monday, November 2, 2015 9:30 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] What's the purpose of stitching vias which just
connect one GND layer?
Hi Guru:
I found one interesting thing on Intel 6-layer(S-VCC-S-S-GND-S) CRB
about the stitching via.
There are pairs of stitching GND via put around the differential
signals(PCIe gen3) transited from TOP to BOTTOM layer.
The differential signal is VCC reference on the TOP layer and GND
reference on the BOTTOM layer.
My understanding for the stitching via is to provide the return path
(GND reference transited to another GND reference) But in the Intel
CRB I had on hand, these stitching vias are only connected to one GND
layer. What's the purpose?
Using capacitor to connect VCC/GND will be better, right?
Best Regards,
Kevin Hou
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