[SI-LIST] Re: ´ð¸´: Re: [SI-LIST]the palcement of bypass/decoupling capacitors
- From: "istvan novak" <istvan.novak@xxxxxxxxxxxxxxxx>
- To: <luhaizhao@xxxxxxxxxx>
- Date: Wed, 22 Jan 2003 07:53:00 -0500
Hi Lu,
By 'well-designed' I meant an impedance profile, which is flat
or close to flat over a wide frequency range. Circuit theory
tells us that flat impedance magnitude versus frequency comes
from resistance. You get more inductive or capacitive portions
of the impedance along frequency only if you allow for bigger
ripple in the impedance profile.
A (close to) flat impedance profile certainly can be achieved in
many different ways. If you achieve it, whether with high-Q or
low-Q capacitors, in either case, you are using mainly the resistive
bottom part of the 'V' shapes.
Regards,
Istvan Novak
SUN Microsystems
----- Original Message -----
From: "lu Haizhao" <luhaizhao@xxxxxxxxxx>
To: <istvan.novak@xxxxxxxxxxxxxxxx>
Cc: <si-list@xxxxxxxxxxxxx>
Sent: Wednesday, January 22, 2003 6:21 AM
Subject: [SI-LIST] ´ð¸´: Re: [SI-LIST]the palcement of bypass/decoupling
capacitors
>
> Hi Istvan,
> When I try to study your comments,I find someting that I can not
> understand well.
> You said "In fact, most well-designed power distribution networks
> will provide neither capacitive nor inductive, but mostly resistive
> impedance over a wide range of frequencies."
> do you mean that we should use bottom of the bypass capacitors 'V"
> shape impedance?and the wider of the bottom of ' V ' shape in frequency
> the better?that is to say,the bottom of the ' V ' shape is resistive
> impedance wo should use,isn't it?
> Thanks!
>
> Regards,
>
> Lu Haizhao
> Huawei Technologies co.,Ltd=20
> Shenzhen China=20
>
>
> -----=D3=CA=BC=FE=D4=AD=BC=FE-----
> =B7=A2=BC=FE=C8=CB: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] =B4=FA=B1=ED istvan novak
> =B7=A2=CB=CD=CA=B1=BC=E4: 2003=C4=EA1=D4=C220=C8=D5 0:37
> =CA=D5=BC=FE=C8=CB: luhaizhao@xxxxxxxxxx
> =B3=AD=CB=CD: si-list@xxxxxxxxxxxxx
> =D6=F7=CC=E2: [SI-LIST] Re: [SI-LIST]the palcement of bypass/decoupling
> capacitors
>
>
>
> Hi,
>
> Similar questions have come up a few times in the past, you can=20
> search the si-list archive (pointer is at the bottom of each posting)
> for previous opinions.
>
> The 'range of bypass capacitor' is one of the popular views in=20
> power distribution design, and it is based on the time of flight=20
> between the capacitor and the device it is supposed to serve. This model
> views the bypass capacitor as a temporary=20
> storage of charge on its way from the DC source to its final=20
> destination. This model, when connected to the series resonance
> frequency of capacitors, also implies and suggests that capacitive
> impedance is 'good' in power distribution, while inductive impedance is
> 'bad'.
>
> While the elements of this model and view may all be correct,
> I would not apply them in general to power distribution designs. The
> device, which we want to power, does not care for the=20
> time of flight of the charge, and it is equally happy if the charge
> comes from inductance, capacitance or resistance. In fact, most
> well-designed power distribution networks will provide neither
> capacitive nor inductive, but mostly resistive impedance=20
> over a wide range of frequencies.
>
> The two extreme possibilities of power distribution designs are=20
> (and a wide range of mix in between) either putting almost all
> components of the network very close to the desitination, or=20
> using grids or planes to feed devices, while bypass capacitors are
> remotely located. We have the first option when we use=20
> very small shapes around the package, or possibly put bypass capacitors
> on the back side of the board under the package,=20
> with no or minimal horizontal connections. In this=20
> case the 'effective radius' of capacitor does not matter. We may=20
> need the second solution when we cannot (or for some other reason we
> dont want to) put bypass capacitors very close to package pins. This
> kind of design usually has paired-up power ground planes and the bypass
> capacitors can be placed further away.
>
> Any time when we go through horizontal connections to feed a package,
> the characteristic impedance of the trace (for low-current=20
> applications) or the characteristic impedance of the planes (for
> high-power applications) should approximately equal the impedance the
> device needs. The traces or planes are transmission lines, we=20
> have to match (terminate) them to get an impedance which will not=20
> wildly fluctuate with frequency. As long as the matching is=20
> achieved, it does not matter how far we have the capacitors from=20
> the package. If we do not have proper matching, the impedance gradiant
> may be huge over very short distances, even within what=20
> we otherwise may call the 'effective radius' of the capacitor. Such
> designs still may work OK, but it takes a lot of simulation to make sure
> that it is acceptable under all circumstances.
>
> In summary, when we try to put capacitors as close to the pins as
> possible, this means that we know that the horizontal plane/trace=20
> connections would be too inductive. The tradeoff is that you can=20
> place bypass capacitors remotely when the horizontal inductance=20
> is low enough, which usually means thin dielectrics, which come=20
> at a higher price. If we do this properly, the location of bypass
> capacitors matters much less and the 'service area' of the bypass=20
> capacitor is mostly irrelevant.
>
> I hope this helps.
>
> Regards,
>
> Istvan Novak
> SUN Microsystems
>
>
>
>
>
> ----- Original Message -----=20
> From: "lu Haizhao" <luhaizhao@xxxxxxxxxx>
> To: <si-list@xxxxxxxxxxxxx>
> Sent: Friday, January 17, 2003 9:51 PM
> Subject: [SI-LIST] [SI-LIST]the palcement of bypass/decoupling
> capacitors
>
>
> >=20
> > Hi,all,
> > I am confusing about the placement of the bypass/decoupling=20
> > capacitors.Xilinx inc has an application note with the name 'Power=20
> > Distribution System (PDS) Design:Using Bypass/Decoupling=20
> > Capacitors'.you can find it from website:=20
> > http://www.xilinx.com/xapp/xapp623.pdf. In the page 8 we can find the=20
> > content about the capacitors palcement,it has a example that a=20
> > capacitor whose effective frequency is 125.8 MHz can place 1.53
> inches(3.8cm) away from the ICs power pin .
> > In other notes,conclusion is that the high frequency bapass=20
> > capacitors shoulb be placed as close as posiible to the IC.The reason=20
> > is to get the lowest inductance.
> > If anynoe have studied about it?Can you tell which one above is=20
> > the truth?
> >=20
> > Lu Haizhao
> >=20
> > Shenzhen,China
> >=20
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