[SI-LIST] Re: Re DDR2 DQS pins
- From: steve weir <weirsi@xxxxxxxxxx>
- To: saira shaikh <saira_pune@xxxxxxxxx>
- Date: Wed, 17 Jun 2009 02:00:49 -0700
Your question is more appropriate the arch.FPGA reflector. If your
problem is you swapped a DQ line with a DQS# line I don't think there is
an answer.
If you mistyped and what you really did is swap a DQS with its matching
DQS# line then the only certain way I know that you could do that is to
manually edit the cell post P&R, save as a different .ncd and then
generate the bit file. The EDK will then be oblivious to your hack.
The downside is that either you save off the I/F as a macro, and then
change your build files to invoke that macro in place of the EDK files
or you will have to repeat the manual edit every time you run the back end.
Steve.
saira shaikh wrote:
> Hi
>
> I am using DDR2 SODIMM of 200 pin interface(2GB) with Virtex5 and it is
> working fine only the problem is with one byte as because of DQ and DQS# (3)
> by mistake these are interchanged while routing the board on DDR2 module. EDK
> is used for DDR2 and it is not allowing in changing UCF file to swap these P
> and N signal. And if it is tried then EDK changing all constraints.
>
> Has any one face this problem and solve it ?
>
> Thanks in Advance
>
> Ms. Saira Shaikh
>
>
>
>
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