[SI-LIST] Re: Raltion between tr to tpd for buffer
- From: "Narayane Manish Shivdas, TLS,Chennai" <manishsn@xxxxxx>
- To: "Gil Simsic (SBC)" <gil.simsic@xxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 28 Mar 2008 18:05:34 +0530
So what should be rule of thumb? Plz reply.
Thanks & regards,
Manish
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Gil Simsic (SBC)
Sent: Thursday, March 06, 2008 9:44 PM
To: Narayane Manish Shivdas, TLS,Chennai; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Raltion between tr to tpd for buffer
Greetings Manish
There is indeed a relationship between the Tpd and the Tr, but in some
IO=20
standards, or IO cells it might be minute and negligible.
Your question is very generic and since you did not point out a specific
standard or technology I will give you my generic analogy -
The Tr defines the change of voltage per time of the input signal to an
IO=20
cell. As all IO cells build of transistors, either CMOS or TTL, they are
bound to the basic rules of - once you pass a specific threshold, you
bias=20
the junction in a way that it will either be active or saturated (I
simplify=20
it of course)
So when the input to an IO cell changes from low to high (i.e. Tr) the=20
various transistors' biasing will change.
So simply putting it, the rate of change (Tr) will dictate how fast they
will move from saturation to active for instance, and through the linear
stage of the Tr there will be a linear influence on those transistors.
Hope it helps
Gil
----- Original Message -----=20
From: "Narayane Manish Shivdas, TLS,Chennai" <manishsn@xxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Thursday, March 06, 2008 7:55 AM
Subject: [SI-LIST] Raltion between tr to tpd for buffer
> Hello All,
>
> I am doing signal integrity analysis. Can I come to know
> the should be relation between the maximum and min propagation delay
of
> the input signal to the buffer propagation delay.
>
>
>
> Thanks & Regards,
>
> Manish
>
>
>
>
>
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