[SI-LIST] Re: ROOKIE: Anti-Pad Size Effect On Signal Integrity: By the formula, as F goes up, Xc goes down (was up by typo)
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: steven.salkow@xxxxxxxx
- Date: Tue, 12 Dec 2006 18:42:56 -0500
Steven
Unfortunately, both the the paper and Dr Johnson's work are accurate
only in the quasi-static domain. Our work on launches has shown that
quasi-static analysis and models for vias are not very useful, except as
a first order approximation. By using full-wave techniques, we can push
via cutoff frequencies up to 40 GHz.
We have a few slides on our website under publications that discuss
high-performance via and launch issues.
*Evaluation of a Single Via in the Frequency Domain
**Hybrid Solver and Measurement Based Design
**Electrically Transparent 50 Gbps Board-to-Board Interconnect
best regards,
Scott
*
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC
Salkow, Steven wrote:
> These links will help
>
>
> characterization_of_a_printed_circuit_board_via
>
>
>
> http://www.coe.montana.edu/ee/lameres/vitae/publications/1_thesis/thesis
> _002_msee.pdf
>
>
>
>
>
> Dr. Johnson constructs a working large scale model of a via, large
> enough so the he can reach into the board and modify the structure from
> within while observing, in real-time, the electrical behavior of the
> via.
>
> http://www.sigcon.com/SiLab/Via_clip.wmv
>
>
>
> 3D field solvers versus Network Analyzer and real models
>
> Many of you are already using coupons to assess the quality of your
> boards. For those they are not familiar, Test coupons are typically
> small sections around the periphery of a board with exactly the same
> layers stackup as the main PCB that are fabricated at the same time as
> the PCB. Coupons are or may be used to test a number of PCB features
> that determine impedance, design integrity, etc.
>
>
>
> The opportunity exists to assess via-model-designs at practically no
> cost to the project other than the via design time and lab assessment to
> characterize the results:
>
> I envision a series of coupon with the various vias and anti-pads as
> well as guard grounds place so these may be connectorized with surface
> mount sma or sna connectors compatible with your Network analyzer. This
> will allow an engineer to extract an S parameter model from each
> physical module which may be useful for further simulation. (Most high
> speed circuit simulators will be able to use S parameter model in
> simulations.) This may seem, on the face of it, an expensive approach.
> In reality, it is cheaper and quicker than 3D field solving but DOES NOT
> produce an exact solution.
>
>
>
> Understand this:
>
> The optimum via design is rarely the one used as board space is not
> available to contain all the signals and all the grounds in the same
> area. As density of vias go up, the ground planes are literally carved
> away near the BGAs where circuit density is the highest. What also goes
> away is exact prediction of circuit behavior without exact 3D modeling
> which is time intensive and uses expensive software tools.
>
>
>
> Steven Salkow
>
> Lockheed IS&S
>
> 3130 Zanker Rd, San Jose
>
> Ca. 94588
>
> steven.salkow@xxxxxxxx
>
> salkow@xxxxxxxxxxxx
>
>
>
>
>
>
>
>
>
> ________________________________
>
> From: chand basha [mailto:chand_374@xxxxxxxxx]
> Sent: Tuesday, December 12, 2006 12:03 AM
> To: Salkow, Steven; PaulClarke@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: Re: [SI-LIST] Re: ROOKIE: Anti-Pad Size Effect On Signal
> Integrity:By the formula, as F goes up, Xc goes down (was up by typo)
>
>
>
>
>
> Steven Salkow,
>
>
>
> its an excellent presentation, very simple really very simple,
>
>
>
> I have a dought in the last para i.e
>
> How do we tune via impedance? We use ground vias nearby and 3D Modeling
> tools that exist to fufill this purpose but that is beyond the scope of
> a short answer.
>
>
>
> if you can explain a littile bit about tuning the impedance with ground
> vias will be very much
>
> help full.
>
>
>
>
>
> Thanks in advance.
>
>
>
> chand
>
>
>
>
>
> "Salkow, Steven" <steven.salkow@xxxxxxxx> wrote:
>
>
>
> -----Original Message-----
> From: Salkow, Steven
> Sent: Monday, December 11, 2006 1:59 PM
> To: 'PaulClarke@xxxxxxxxxxxxx'; 'si-list@xxxxxxxxxxxxx'
> Subject: RE: [SI-LIST] ROOKIE: Anti-Pad Size Effect On Signal
> Integrity
>
> Paul:
> I will make this simple are seems reasonable. It does, however,
> seem to
> me quite extraordinary that a mechanical fellow might be getting
> involved with Gigahertz design of vias.
>
> You're correct the effect does depend on speed. The "anti-pad"
> is used
> when building plane layers (i.e.: solid layers) using negative
> planes.
> It is the VOID area between the pad and the copper of the plane.
> The
> effect is to provide a capacitive reactive effect given by the
> formula
> Xc= 1/(2*pi*F*C) where f is frequency and C is capacitance. By
> the
> formula, as F goes up, Xc goes down (was up by typo). The C
> capacitance
> is given by the formula C = (Area*k*e)/length where length is
> really the
> distance the two areas are apart (in this case the width of the
> anti-pad
> (the bigger the gap, the smaller the capacitance). The effects
> of C is
> cumulative for multiple planes.
>
> If the anti-pad size is very large, are we out of the woods. NO!
> All signals used in modern design as transmission lines have a
> certain
> desirable impedance. The is the effective "resistance" of the
> line that
> best matches the driver electronics. When effective "resistance"
> of the
> line does not match the driver electronics one of two
> possibilities
> happen:
> The signal has energy reflected back to the source
> Or excessive energy is absorbed by the circuit a too little gets
> to the
> load.
> Anti-pads are designed to maintain the required effective
> "resistance"
> (impedance) of a transmission line at a matching value. What's
> that
> mean?
> If the line impedance and the driver impedance and the load
> impedance
> are all 50 ohms, then the via should be tuned to the same value.
>
> How do we tune via impedance? We use ground vias nearby and 3D
> Modeling
> tools that exist to fufill this purpose but that is beyond the
> scope of
> a short answer.
>
> Steven Salkow
> Lockheed IS&S
> 3130 Zanker Rd, San Jose
> Ca. 94588
> steven.salkow@xxxxxxxx
> salkow@xxxxxxxxxxxx
>
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Clarke, Paul
> Sent: Monday, December 11, 2006 1:25 PM
> To: 'si-list@xxxxxxxxxxxxx'
> Subject: [SI-LIST] ROOKIE: Anti-Pad Size Effect On Signal
> Integrity
>
> Hello,
>
> Before you read the question please keep in mind that I am just
> a lowly
> Mechanical guy that has better odds of selecting the right bolt
> than I
> do
> designing an LED circuit.
>
> I have a question about how the size of an anti-pad can effect
> signal
> integrity. The example application could be a backplane @ 5, 10,
> 20, 40,
> or
> 80 [G] (I am asking for this range because I anticipate the
> answer may
> depend on the speed).
>
> If you have a BP via for a signal pair of .025" with a pad of
> .044", how
> much impact can an antipad have on the impendance through a
> range of
> sizes
> of let's say .054-.060"? Center-Center distance could be 2.1
> [mm].
>
> In the case described above, would the antipad size range really
> have
> any
> effects or is it negligible?
> Is an anti-pad just to keep solder off the pad if you flood the
> plane?
> Or is
> there an actual SI reason for those things?
> How sensitive is the SI to changes in antipad size?
> Any concerns regarding manufacturing tolerances on antipads?
>
> Thank you for any information and your patience explaining any
> of the
> above
> questions to a mechanical guy.
>
> Paul Clarke
>
>
>
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