[SI-LIST] Re: RGMII length match guide lines
- From: "Peter zhu" <yonghui.sky@xxxxxxxxx>
- To: "Eric Tran \(ertran\)" <ertran@xxxxxxxxx>, "shivaraj k" <shivaraj.k@xxxxxxxxxxx>, <si-list-bounce@xxxxxxxxxxxxx>
- Date: Thu, 19 Nov 2009 00:18:15 +0800
Hi Shivaraj,
keep TX data/TX clk same length, RX data/RX clk same length, should be ok for
most of MAC/PHY.
But usually, the data/clk skew of most RGMII interface of MAC/PHY chip can be
set through register. You can check the datasheet.
Peter Zhu
Emerson Network Power
--------------------------------------------------
From: "Eric Tran (ertran)" <ertran@xxxxxxxxx>
Sent: Wednesday, November 18, 2009 6:40 AM
To: "shivaraj k" <shivaraj.k@xxxxxxxxxxx>; <si-list-bounce@xxxxxxxxxxxxx>
Cc: <si-list@xxxxxxxxxxxxx>
Subject: [SI-LIST] Re: RGMII length match guide lines
> Hi Shivaraj,
>
> Clock skew depends on Thld, Tsu of the TX and RX. Are you skewing to
> maximize margins? Or just enough to get it work?
>
> Eric
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of shivaraj k
> Sent: Tuesday, November 17, 2009 4:03 AM
> To: si-list-bounce@xxxxxxxxxxxxx
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] RGMII length match guide lines
>
> Hi,
>
> What is the extra clock length need to be routed in case of RGMII
> interface.
> The setup time is 1ns and hold time 1ns
>
> Regards
>
> Shivaraj k
>
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