[SI-LIST] Re: REPOST: SI Question 2 of 3: Differential clock lines over split in ground plane
- From: steve weir <weirsi@xxxxxxxxxx>
- To: jpcoetzee@xxxxxxxx, <si-list@xxxxxxxxxxxxx>
- Date: Mon, 31 Oct 2005 10:00:35 -0800
Now you really want a drawbridge, or else extra time in the compliance lab
with an expensive consultant. See any of Doug Smith's excellent pieces on
the implications of crossing a discontinuity with differential signals.
Steve.
At 09:33 AM 10/31/2005 +0000, John-Paul Coetzee wrote:
>Reposted to try and make the diagram clearer!=20
>
>Same system as described in Question 1.
>
>There are also two differential LVPECL clock traces providing a 75MHz =
>clock to an ADC in the Analog section. This pair crosses the slot about =
>halfway along its length. The ADC sits on the junction of the Digital =
>and Analog ground planes.=20
>
>What are the risks of the differential traces crossing the slot? =
>Particularly with respect to degradation of noise margin in the analog =
>zone.
>
>
>| ######### D I G I T A L G R O U N D
>| #########
>| #########
>| +-------+######### +----------------------
>| | |######### | =20
>| | |######### | S L O T =20
>| | |### ### | =20
>| | S |### W ### +----------------------
>| | |### ### =20
>| | L |### A ### =20
>| | |### ###
>| | O |### L ###
>| | |### ###
>| | T |### L ### A N A L O G G R O U N D
>| | |### ###
>| | |#########
>| | |#########
>| --------------------#########--------------------- Diff+
>| | |#########
>| --------------------#########--------------------- Diff-
>| | |#########
>| | |#########
>| | |#########
>| | |#########
>| | |#########
>| | |#########
>| +-------+#########
>| #########
>| #########
>| #########
>+----------------------------------------------------------------
>
>--
>JP Coetzee (was JP Nicholls) / jpcoetzee@xxxxxxxx
>
>Digital Design Engineer
>
>Powerwave UK Ltd
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