[SI-LIST] R: Re: Serpentine patterns for length matching
- From: <gianguida@xxxxxxxx>
- To: <wolfgang.maichen@xxxxxxxxxxxx>
- Date: Fri, 24 Oct 2008 13:18:17 +0200
Hi all,
this is a perfect application for the usage of
a combination of 3D EM and RF circuit simulator.
(just to make an example, CST Microwave studio and CSTDesign studio)
Use the 3D simulator and perform a parametric analysis of your serpentine layout
changing distance, lenght...
and then use the parametric model in the circuit simulator
to perfom time domain analysis.
In this way it is easily possible to obtain both guideline s
for your layout and/or accurate postlayout verification.
Hope this helps
Giancarlo
________________________________
Da: si-list-bounce@xxxxxxxxxxxxx per conto di wolfgang.maichen@xxxxxxxxxxxx
Inviato: gio 23/10/2008 21.59
A: wolfgang.maichen@xxxxxxxxxxxx
Cc: otter30@xxxxxxxxxxxxx; SI-List; si-list-bounce@xxxxxxxxxxxxx
Oggetto: [SI-LIST] Re: Serpentine patterns for length matching
A short correction - of course it should be "parasitic CAPACITANCE of the
bends", not "inductance"!
Wolfgang
wolfgang.maichen@xxxxxxxxxxxx
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[SI-LIST] Re: Serpentine patterns for length matching
Jim,
parasitic inductance of the bends is a secondary effect with typical trace
dimensions (<20mil trace width). What is more of a concern is the tight
spacing you mention, which will cause significant crosstalk. The main
effect of that will be that your actual delay through the serpentine will
be LESS than what you'd expect given the geometric line length, dielectric
constant etc. A simple picture is to think of part of the signal taking a
shortcut hopping straight from segment to segment instead of following the
trace. A closer investigation shows that in addition this also causes
distortion of the output waveform, which is another undesired effect.
Secondary corrections are current crowding at the in side if the bend
(again lowering the prop delay) etc., but first you want to get the basic
layout right.
To reduce the effect of the bends (which each adds a small amount of
parasitic capacitance, and if there are many bends even small
contributions can add up), simply use two 45 degree bends instead of a
single 90 degree bend, that gives you most of the necessary correction
without the need to do any simulation.
The simplest way to correct your layout is to require a spacing of about
3x the line width for striplines, or 5 - 6x the line width for surface
microstrips. This effecteively reduces crosstalk to well below 1%.
If out of some reason you absolutely can't increase the line-to-line
spacing, at least make each line segment shorter that about 1/6th of your
signal rise time to minimize signal distortion. In this case you'll need
to use a 2.5D or 3D field solver to figure out how much your delay is
reduced and then correct for that by adding more trace length.
(Alternatively, manufacture a small test board with a single serpentine
line, measure its delay and thus determine the correction factor
experimentally).
Wolfgang
otter30@xxxxxxxxxxxxx
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10/23/2008 08:21 AM
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[SI-LIST] Serpentine patterns for length matching
Hello,
Does anyone know of general guidelines for the serpentine patterns used to
match net lengths?
We have a board with lots of diff pairs, and our board designer made the
serpentines very
tight. The separation between the adjacent bends of a pair is the same as
the spacing of the
traces in the pairs themselves. This seems to imply imedance variations if
the trace widths
don't change in the bends.
Any insights would be greatly appreciated,
Jim
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