[SI-LIST] Re: R: Re: R: digital core model
- From: Yafei Bi <yafei_bi@xxxxxxxxx>
- To: saoer.sinaga@xxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Wed, 29 Nov 2006 08:41:11 -0800 (PST)
Take a look at Apache Design Automation, they offer the best solutions to b=
ridge IC design and Signal Integrity Issues on the market. =0A=0Ahttp://www=
.apache-da.com/html/products_solutions/products_solutions.htm=0A=0Ap.s.: I =
am not associated with Apache. You may want to do your own due-diligence.=
=0A=0ABest=0A=0AYafei=0A=0A----- Original Message ----=0AFrom: Saoer Sinaga=
<saoer.sinaga@xxxxxxxxx>=0ATo: si-list@xxxxxxxxxxxxx=0ASent: Wednesday, No=
vember 29, 2006 8:14:57 AM=0ASubject: [SI-LIST] Re: R: Re: R: digital core =
model=0A=0AThanks a lot for the suggestion. But can you suggest anything ot=
her than=0Atransistor-level model? What do you think of a kind of norton e=
quivalent=0Acurrent model which basically a current source in parallel with=
capacitor,=0Aand then using triangular shape current waveform?=0AI used to=
get support from Ansoft in UK. I don't remember if we were ever in=0Aconta=
ct.=0A=0Asaoer=0A=0AOn 11/29/06, gianguida@xxxxxxxx <gianguida@xxxxxxxx> wr=
ote:=0A>=0A> If you have a really good circuit simulator=0A> able to analys=
e very large netlist in a resonable=0A> amount of time=0A> the combined usa=
ge of transistor level model for the die=0A> and em simulation ( 3D in my p=
ersonal opinion)=0A> to model the interconnection will give you=0A> the bes=
t results=0A> Giancarlo=0A>=0A> P:S: did we exchange some email... time ago=
when I worked for Ansoft?=0A>=0A>=0A> -----Messaggio originale-----=0A> Da=
: si-list-bounce@xxxxxxxxxxxxx per conto di Saoer Sinaga=0A> Inviato: mer 2=
9/11/2006 14.31=0A> A: si-list@xxxxxxxxxxxxx=0A> Oggetto: [SI-LIST] Re: R: =
digital core model=0A>=0A> Dear Giancarlo,=0A> Thanks for the reply.=0A> I =
would like to do something like SSN simulation, also try to optimize my=0A>=
PDN.=0A> I have resources to do EM simulation (2D, 2.5D, 3D), circuit simu=
lation,=0A> etc.=0A>=0A> saoer=0A>=0A>=0A> On 11/29/06, gianguida@xxxxxxxx =
<gianguida@xxxxxxxx> wrote:=0A> >=0A> > dear Saoer,=0A> > the answer to you=
r question=0A> > depends on=0A> > 1) what effects you need to model=0A> > 2=
) what simulation resources you have to use the model=0A> > 3) what is the =
accuracy you need to achieve=0A> > may be you may want to better specify yo=
ur needs.=0A> >=0A> > Regards=0A> > Giancarlo=0A> >=0A> > -----Messaggio or=
iginale-----=0A> > Da: si-list-bounce@xxxxxxxxxxxxx per conto di Saoer Sina=
ga=0A> > Inviato: mer 29/11/2006 10.25=0A> > A: si-list@xxxxxxxxxxxxx=0A> >=
Oggetto: [SI-LIST] digital core model=0A> >=0A> > Hi all,=0A> > I want to =
do System in Package modeling. The SiP is laminate based,=0A> > and consist=
s of several active silicon dies. What kind of model should I=0A> > use=0A>=
> for those active dies? Should I use transistor-level model? or should I=
=0A> > use=0A> > the current profile information? or just a simple norton e=
quivalent core=0A> > model?=0A> >=0A> > Anyone could give me an idea? or pe=
rhaps refer some papers or books?=0A> >=0A> > thanks a lot,=0A> > Saoer=0A>=
>=0A> >=0A> > ------------------------------------------------------------=
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