[SI-LIST] Re: R: How to Route XFP 10G electrical trace?

  • From: "QU Perry" <Perry.Qu@xxxxxxxxxxxxxxxxxx>
  • To: "SI-List" <si-list@xxxxxxxxxxxxx>
  • Date: Fri, 16 Mar 2007 11:00:52 -0500

Quite a few posts mentioned about 3D full wave simulation on this, but
what you get from that is the insertion loss for the link. How will that
tell you whether you have acceptable eye or not at receiver ? On MSA
spec it mentioned that we need to have IL< 9.6dB at 5.5GHz and for a
short run on microstrip with or without via, the IL won't be no where
near that number. What 3D sim can tell is how IL of one scheme perform
against another but it won't tell whether the good one is good enough.
To close the loop, we really need to do some time domain simulation with
Tx/Rx Spice model and get the eye diagram at the receiver. The problem
is no XFP vendor seems to provide any models for their device.

Regards

Perry

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Perry Qu=20

Design & Qualification, Alcatel-Lucent Canada Inc.

600 March Road, Ottawa ON, K2K 2E6, Canada=20

DID: 613-7846720  Fax: 613-5993642=20

Email: perry.qu@xxxxxxxxxxxxxxxxxx=20

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-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Javier DeLaCruz
Sent: Friday, March 16, 2007 1:55 AM
To: SI-List
Subject: [SI-LIST] Re: R: How to Route XFP 10G electrical trace?

I agree that you will have a hard time getting this to work properly
without some full-wave simulation.  Given that you are routing on the
top layer, you will have the benefit of less dialectic loss from the air
above the PCB.  Having this in microstrip does take up slightly more
space since you typically need to have wider traces to achieve an
certain impedance as compared to stripline.  That hurts if it is a high
density design but it helps otherwise since the variation in etching
should have less of an effect on a wider trace as a percentage.
Additionally, the lower dielectric loss of microstrip mode (assuming air
and thin soldermask above it) will help as I mentioned earlier.  The
fact that you are not going through a via in option 1, will help.  Vias
always pose a significant discontinuity unless you use expensive via
design rules, so I would avoid your second option.  I want to avoid
giving a rule of thumb on this since it is dangerous to use such a rule
at 10G, but you should plan on having many shielding vias adjacent to
the traces to your power supplies.  Self resonance of the transmission
lines is something to watch out for at these frequencies.  Plan on
simulating this, or outsourcing this simulation since the software can
be pricey.

Regards,
Javier DeLaCruz
=3D20

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Jim Whitehead
Sent: Friday, March 09, 2007 2:47 PM
To: SI-List
Subject: [SI-LIST] Re: R: How to Route XFP 10G electrical trace?

I would definitely kick off a simulation effort.  Keep in mind that with
microstrips it is much harder to control the impedance of those
outer-layer traces, in the fabrication process.  Also, care should be
taken if routing through the ground area on the top layer and when going
under the the cage; both are opportunities for impedance
discontinuities.

Cheers,

Jim

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of gianguida@xxxxxxxx
Sent: Friday, March 09, 2007 1:28 AM
To: Yee.Chung@xxxxxxxxxxxxxxxxxx; SI-List
Subject: [SI-LIST] R: How to Route XFP 10G electrical trace?

A prefect case to use a simulations to judge between several choices.
Use a 3D trool suca CST Microwave studio could be quite useful Hope this
help Giancarlo ________________________________

Da: si-list-bounce@xxxxxxxxxxxxx per conto di CHUNG Yee
Inviato: gio 08/03/2007 18.14
A: SI-List
Oggetto: [SI-LIST] How to Route XFP 10G electrical trace?



Hi all,
I would like to get some opinions on how people route the electrical 10G
traces.

I am using FR4 and I don't plan no using any fancy via technologies such
as blind via.

I am looking into two options:

1, 100 ohm microstrip on top layer only, directly from the XFP connector
to the PHY's BGA. However, it seems to me that this routing method is
violated the XFP MSA spec in the figure 35 (XFP host board mechanical
layout). I need to cut two gaps from the rear of cross-hatched area in
order to escape the 10G signals and these signal will be covered by
solder-mask. Based on internal discussion, we have some concern on the
rear EMI gasket of the XFP cage that might scratch-off the solder-mask
over time due to vibration hence short these traces to Gnd! However, I
have check various vendors test board and even the Intel reference test
board in the XFP MSA are using this method!

2, Use via to bottom layer and then 100 ohm microstrip on bottom layer
to the PHY's BGA.

Any feedback will be much appreciated!

Yee








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