[SI-LIST] R: How to Route XFP 10G electrical trace?
- From: <gianguida@xxxxxxxx>
- To: <Yee.Chung@xxxxxxxxxxxxxxxxxx>, "SI-List" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 9 Mar 2007 10:27:42 +0100
A prefect case to use a simulations to judge
between several choices.
Use a 3D trool suca CST Microwave studio
could be quite useful
Hope this help
Giancarlo
________________________________
Da: si-list-bounce@xxxxxxxxxxxxx per conto di CHUNG Yee
Inviato: gio 08/03/2007 18.14
A: SI-List
Oggetto: [SI-LIST] How to Route XFP 10G electrical trace?
Hi all,
I would like to get some opinions on how people route the electrical 10G
traces.
I am using FR4 and I don't plan no using any fancy via technologies such
as blind via.
I am looking into two options:
1, 100 ohm microstrip on top layer only, directly from the XFP connector
to the PHY's BGA. However, it seems to me that this routing method is
violated the XFP MSA spec in the figure 35 (XFP host board mechanical
layout). I need to cut two gaps from the rear of cross-hatched area in
order to escape the 10G signals and these signal will be covered by
solder-mask. Based on internal discussion, we have some concern on the
rear EMI gasket of the XFP cage that might scratch-off the solder-mask
over time due to vibration hence short these traces to Gnd! However, I
have check various vendors test board and even the Intel reference test
board in the XFP MSA are using this method!
2, Use via to bottom layer and then 100 ohm microstrip on bottom layer
to the PHY's BGA.
Any feedback will be much appreciated!
Yee
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