[SI-LIST] Re: Questions on Reference Planes for DDR3 signals
- From: steve weir <weirsi@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 17 Jul 2012 10:10:27 -0700
Vinu, any examination of the voltage potential at the die side of Vss,
or the die side of Vdd will show that each suffers SSO. Take any planar
cross-section through a schematic representation of the die to the
package or anywhere in the interconnect and KCL still applies: The net
current into the slice is the same as out of the slice. When the signal
bus is not by itself balanced to exhibit zero switching current, the
returns into the package will between them, and no matter what the
configuration, divide the corresponding complementary current. In order
to cancel SSO, the return currents have to cancel. They do not cancel.
They divide between the rail, or rails used based on the number of and
effective inductance of interconnects used between the board that the
package, or going up the chain: the package and the die.
Steve.
On 7/17/2012 9:49 AM, Vinu Arumugham wrote:
> Steve,
>
> "That's all fine and well but does nothing for SSO as seen by the transmitter
> die, or the noise
> injected into the cavity."
>
> v(Vddq,Vssq) is the transmitter die noise (SSN) and it is only a few mVpp
> with SRS and much larger with Vss-only reference. v(Vddq,Vssq) is also the
> noise injected into the cavity ( a few mVpp). One can observe the other end
> of the cavity v(termVdqq,termVssq) and also observe only a few mVpp with SRS.
>
> For a Vss-only referenced transmission line, a Thevenin termination would
> require a low impedance PDN to work. In SRS you may have noted that there is
> no low impedance PDN between termVddq and termVssq. Do you have a topology in
> mind that uses Thevenin termination alone without SRS and can achieve
> constant current draw from the PDN? You could post a modification to the
> spice deck if that helps avoid any misunderstanding.
>
> Thanks,
> Vinu
>
>
> On 07/16/2012 06:03 PM, steve weir wrote:
>> Well, the few mV of noise are WRT current drawn through the power
>> supply's series inductance. With Thevenin termination and matched
>> electrical lengths in both the effective Tx lines, the power source on
>> the PCB sees a relatively constant current load of Vdd / 2*Zterm as one
>> or the other of the MOSFETs shorts one or the other of the termination
>> resistors from transmit side of the channel. That's all fine and well
>> but does nothing for SSO as seen by the transmitter die, or the noise
>> injected into the cavity. It's the Thevenin termination and not
>> symmetric referencing of the signal to each of the two power rails that
>> is responsible for the nearly constant current seen by the PCB level PDN.
>>
>> Steve.
>>
>> On 7/16/2012 11:35 AM, Vinu Arumugham wrote:
>>> On Scott's request I put together a spice deck. It is configured for
>>> SRS. v(Vddq,Vssq) and v(termVddq,termVssq) show a few mVpp of noise.
>>> There's only a 20pF capacitor between Vddq and Vssq to handle spikes
>>> caused by the non-ideal pullup/down switches.
>>> One can comment the WSRS line, uncomment the WGndRef line and change
>>> rterm2 to 50 ohm to simulate the Vss-only referenced case. v(Vddq,Vssq)
>>> noise is much greater in this case, demonstrating the need for a robust
>>> low impedance PDN.
>>>
>>> v(sout,Vssq) is the signal waveform at the TX, v(termout,termVssq) is
>>> the signal waveform at the RX.
>>>
>>> Spice:
>>> *
>>> * Compare Symmetrically Referenced Signaling (SRS)
>>> * to conventional Vss only referenced signaling
>>> *
>>>
>>> .trans 0.01ns 10ns
>>> .print v(termout,termVssq)
>>> .print v(out,Vssq)
>>> .print v(sout,Vssq)
>>> .print v(Vddq,Vssq)
>>> .print v(termVddq,termVssq)
>>>
>>> * Two pulse sources to drive the pullup and pull down switches
>>> v1 1 0 pulse 0 1 0ns 0.01ns 0.01ns 2ns 5ns
>>> v2 2 0 pulse 1 0 0ns 0.01ns 0.01ns 2ns 5ns
>>>
>>> * Pull up switch
>>> gpu pu Vddq vcr 1 0 1000
>>> rpu pu out 50
>>>
>>> * Pull down switch
>>> gpd pd Vssq vcr 2 0 1000
>>> rpd pd out 50
>>>
>>> * On-die capacitance between Vddq and Vssq
>>> c1 Vddq Vssq 20p
>>>
>>> * Inductor in series with battery to make battery AC "open circuit"
>>> l1 Vddq battpos 1e-3
>>>
>>> vbattery battpos battneg 2
>>> r2 Vssq battneg 1e-3
>>>
>>> .option post=2 post_version=2001
>>>
>>> * Stack up for W-element
>>> .MATERIAL diel_2 DIELECTRIC ER=4 LOSSTANGENT=0.02
>>> .SHAPE rect RECTANGLE WIDTH=10mil,
>>> + HEIGHT=30mil
>>>
>>> .LAYERSTACK stack_1,
>>> + LAYER=(PEC,1mil), LAYER=(diel_2,1200mil),
>>> + LAYER=(PEC,1mil)
>>>
>>>
>>> .MODEL tline W MODELTYPE=FieldSolver,
>>> + LAYERSTACK=stack_1,
>>> + RLGCFILE=ex1.rlgc
>>> + CONDUCTOR=(SHAPE=rect, ORIGIN=
>>> + (50mil,150mil)),
>>> + CONDUCTOR=(SHAPE=rect,
>>> + ORIGIN=(50mil,200mil)),
>>> + CONDUCTOR=(SHAPE=rect, ORIGIN=
>>> + (50mil,250mil))
>>>
>>> rout out sout 50e-3
>>>
>>> * W-element connected in SRS configuration
>>> WSRS Vddq sout Vssq 0 termVddq termout termVssq 0 FSmodel=tline
>>>
>>> * Same w-element connected as conventional Vss-only referenced line
>>> *WGndRef Vssq sout Vssq 0 termVssq termout termVssq 0 FSmodel=tline
>>> +N=3 l=4000mil
>>>
>>> * Termination resistors
>>> * Change rterm2 to 50 for Vss-only case
>>> rterm1 termVddq termout 100
>>> rterm2 termout termVssq 100
>>>
>>>
>>> * Same w-element used to verify line impedance is ~50 ohm.
>>> Wztst 0 5 0 0 0 floatout 0 0 FSmodel=tline
>>> +N=3 l=4000mil
>>> rsrs 1 5 50
>>> .end
>>>
>>> Schematic:
>>> https://docs.google.com/open?id=0B1SXvUJqinZYSHBiNWRNeGZGYjQ
>>>
>>> Thanks,
>>> Vinu
>>>
>>>
>>> On 07/15/2012 08:33 PM, Liuluping wrote:
>>>> Thanks Chris, your explain Is very helpful, especially the sampling
>>>> point problem.
>>>>
>>>> Also thanks to Steve ,Vinu ,Scott and all the experts, though not full
>>>> understand ,but your discussion is very wonderful, may be the
>>>> symmetrically referencing both Vdd and Vss in a push pull driver
>>>> system can¡¯t cancel the SSO to zero due to the unequal inductance ,
>>>>
>>>> But it may reduce the SSO noise close to zero , I thought that¡¯s the
>>>> original purpose which a demo boards design from a Top IC vendor,
>>>> who¡¯s application notes strongly recommend the DDR3 signal should
>>>> symmetrically referencing both Vdd and Vss.
>>>>
>>>> I also search the in the web ,the oldest paper about this topic I can
>>>> get is:
>>>>
>>>> Modeling of simultaneous switching noise in high speed systems
>>>>
>>>> Sungjun Chun; Swaminathan, M.; Smith, L.D.; Srinivasan, J.; Zhang Jin;
>>>> Iyer, M.K.
>>>>
>>>> Advanced Packaging, IEEE Transactions on
>>>>
>>>> Publication Year: 2001 , Page(s): 132 ¨C142
>>>>
>>>> Which was referd in Madhavan and A.Ege¡¯s ¡°Power integrity modeling and
>>>> design for semiconductors and systems¡±,chapter 3.
>>>>
>>>> It shows that the return current flow in the vdd plane when signal
>>>> transition from low to high (unterminal signal),
>>>>
>>>> when signal from high to low , the current in the signal line will
>>>> flow into the GND plane.
>>>>
>>>> So a intuitive thought was why not use a symmetrically referencing
>>>> both Vdd and Vss to reduce the reference plane transition, in order to
>>>> reduce the SSO noise?
>>>>
>>>> Thanks again to all the experts, and sorry to Hirshtal that borrow
>>>> your questions £º£©
>>>>
>>>> LIU Luping
>>>>
>>>> ·¢¼þÈË: Cheng, Chris [mailto:chris.cheng@xxxxxx]
>>>> ·¢ËÍʱ¼ä: 2012Äê7ÔÂ13ÈÕ9:51
>>>> ÊÕ¼þÈË: Liuluping
>>>> ³ËÍ: si-list@xxxxxxxxxxxxx
>>>> Ö÷Ìâ: RE: Questions on Reference Planes for DDR3 signals
>>>>
>>>> Luping,
>>>>
>>>> Sorry for the delay, work has been busy.
>>>>
>>>> I do believe the high speed current loop will always come from the on
>>>> die decoupling but that doesn't mean reference plane optimization is
>>>> not important.
>>>>
>>>> How tight you control the reference plane w.r.t. the signal path
>>>> determines how strong a mutual term you can get to lower your overall
>>>> signal path loop inductance. Which is a di/dt issue, not a decoupling
>>>> issue.
>>>>
>>>> As for the odd mode vs. even mode SSO, you are assuming the ringing is
>>>> settled within one cycle and the perfect sampling point is in the
>>>> middle of UI. In simulations and as in real life, we observed the
>>>> optimal sampling point is slightly later than 1/2 UI. That makes an
>>>> odd mode "pull in" more problematic than an even mode "push out"
>>>>
>>>> HTH
>>>>
>>>> Chris Cheng
>>>>
>>>> Distinguished Technologist , Electrical
>>>>
>>>> Hewlett-Packard Company
>>>>
>>>> +1 510 413 5977 / Tel
>>>>
>>>> chris.cheng@xxxxxx / Email
>>>>
>>>> 4209 Technology Dr
>>>>
>>>> Fremont, CA 94538
>>>>
>>>> USA
>>>>
>>>> -----Original Message-----
>>>>
>>>> From: Liuluping [mailto:liuluping@xxxxxxxxxx]
>>>>
>>>> Sent: Wednesday, June 27, 2012 10:58 PM
>>>>
>>>> To: Cheng, Chris
>>>>
>>>> Cc: si-list@xxxxxxxxxxxxx
>>>>
>>>> Subject: RE: Questions on Reference Planes for DDR3 signals
>>>>
>>>> Hi Chris:
>>>>
>>>> Sorry for resend again.
>>>>
>>>> What puzzle me is when the DDR3 run up to 2133Mbps,certainly we will
>>>> face >1GHz noise on the power plane, does the current loop at this
>>>> frequency should go through the die caps instead of the package caps?
>>>> It means that we have nothing to do to lower the noise at this
>>>> frequency ,include the reference plane optimize discussing now?
>>>>
>>>> As the odd mode pattern problem, I also do some calculations, for
>>>> Zuncoupled=(L/C)^0.5,Zodd=((L-Lm)/(C+Cm))^0.5,Zeven=((L+Lm)/(C-Cm))^0.5,if
>>>> Zuncoupled=50ohm(microstripline),Zodd~49ohm,Zevev~71ohm respectively,
>>>> seens the odd pattern should better at the reflection due to impedance
>>>> mismatch,
>>>>
>>>> but what we got is that the odd mode pattern have more noise
>>>> (~100mV@DDR3) than the even mode pattern.
>>>>
>>>> Thanks and regards,
>>>>
>>>> LIU Luping
>>>>
>>>
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