[SI-LIST] Re: Questions on Reference Planes for DDR3 signals
- From: Liuluping <liuluping@xxxxxxxxxx>
- To: "chris.cheng@xxxxxx" <chris.cheng@xxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Mon, 16 Jul 2012 05:51:36 +0000
Sorry for resend:
发送时间: 2012年7月16日 11:34
收件人: 'Cheng, Chris'; 'steve weir'; 'Vinu Arumugham'; 'Scott McMorrow'
抄送: si-list@xxxxxxxxxxxxx
主题: Re: Questions on Reference Planes for DDR3 signals
Thanks Chris, your explain Is very helpful, especially the sampling point
problem.
Also thanks to Steve ,Vinu ,Scott and all the experts, though not full
understand ,but your discussion is very wonderful, may be the symmetrically
referencing both Vdd and Vss in a push pull driver system can’t cancel the SSO
to zero due to the unequal inductance ,
But it may reduce the SSO noise close to zero , I thought that’s the original
purpose which a demo boards design from a Top IC vendor, who’s application
notes strongly recommend the DDR3 signal should symmetrically referencing both
Vdd and Vss.
I also search the in the web ,the oldest paper about this topic I can get is:
Modeling of simultaneous switching noise in high speed systems
Sungjun Chun; Swaminathan, M.; Smith, L.D.; Srinivasan, J.; Zhang Jin; Iyer,
M.K.
Advanced Packaging, IEEE Transactions on ,Publication Year: 2001 , Page(s): 132
?C 142
Which was refered in Madhavan and A.Ege’s “Power integrity modeling and design
for semiconductors and systems”, chapter 3.
It shows that the return current flow in the vdd plane when signal transition
from low to high (unterminal signal),
when signal from high to low , the current in the signal line will flow into
the GND plane.
So a intuitive thought was why not use a symmetrically referencing both Vdd and
Vss to reduce the reference plane transition, in order to reduce the SSO noise?
Thanks again to all the experts, and sorry to Hirshtal that borrow your
questions ：）
LIU Luping------------------------------------------------------------------
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