[SI-LIST] Re: Question on Impedance Control
- From: "Nirmal Sharma" <nsharma@xxxxxxxxxxxx>
- To: <Pat_Diao@xxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 20 Mar 2003 13:20:59 -0800
Pat;
Using approach #3 we have designed several RX/Tx pairs with wirebond =
that have=20
bettr than 15db retuen loss at 15Ghz, It takes mulitiple iterations to =
get down=20
to the performance that is expected from Flip chip.=20
-----Original Message-----
From: Pat Diao [mailto:Pat_Diao@xxxxxxxx]
Sent: Thursday, March 20, 2003 10:49 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Question on Impedance Control
I think enough has been discussed about using a 2D solver to determine =
the
trace W/S and di-e thickness to achieve the desired impedance - =
single-ended
or differencial.
However, in a real package other than flipchip/CSP, bond wires are =
needed
for the die to traces connection. As such, no matter how well it is
controlled on the traces, the presence of bond wire will always throw =
the
impedance off (usually higher).
So here are the questions about how this is handled in practice:
1. Design the traces to the targeted 50 or 100 ohm and ignore the effect =
of
wires, hoping for the best?
2. Pre-lower the trace impedance in design in anticipating the effect of
wire?
3. Use 3D simulation on the designed wire + trace struction to calculate =
the
actual impedance?
Feedback appreciated.
Pat=20
Pat Diao
ASAT
Fremont, CA
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