[SI-LIST] Re: Question on Impedance Control
- From: "Bill Beale" <beale@xxxxxxxxxxxxxx>
- To: <Pat_Diao@xxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 20 Mar 2003 11:04:39 -0800
Hi Pat,
In your choices, you're making a large assumption, which is: 50 ohm =
impedance is desired up to the die. I've worked on chips which =
'like/want' slightly more inductance before the die to offset the =
capacitance of the pad and gate of the high speed receiver. Hence, the =
answer to your question is dependent on your application.
Without knowing the application, I would vote for #1, and determine my =
bondwire configuration after I know more about the impedance looking =
into my die.
Thank you,
Bill
> I think enough has been discussed about using a 2D solver to=20
> determine the
> trace W/S and di-e thickness to achieve the desired impedance=20
> - single-ended
> or differencial.
>=20
> However, in a real package other than flipchip/CSP, bond=20
> wires are needed
> for the die to traces connection. As such, no matter how well it is
> controlled on the traces, the presence of bond wire will=20
> always throw the
> impedance off (usually higher).
>=20
> So here are the questions about how this is handled in practice:
>=20
> 1. Design the traces to the targeted 50 or 100 ohm and ignore=20
> the effect of
> wires, hoping for the best?
> 2. Pre-lower the trace impedance in design in anticipating=20
> the effect of
> wire?
> 3. Use 3D simulation on the designed wire + trace struction=20
> to calculate the
> actual impedance?
>=20
> Feedback appreciated.
>=20
> Pat=20
>=20
>=20
> Pat Diao
> ASAT
> Fremont, CA
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