[SI-LIST] Re: Question about jitter at serdes transmitter
- From: "Jory McKinley" <dmarc-noreply@xxxxxxxxxxxxx> (Redacted sender "jory_mckinley@xxxxxxxxx" for DMARC)
- To: "edisonzheng@xxxxxxxx" <edisonzheng@xxxxxxxx>, "joel@xxxxxxxxxx" <joel@xxxxxxxxxx>, SI-List <si-list@xxxxxxxxxxxxx>
- Date: Wed, 18 Feb 2015 04:54:29 +0000 (UTC)
Hello Joel,For SATA3 there are compliance points that are separated in terms of
TX/RX Host, CIC channel, and then TX/RX Device. Â If you are measuring 0.2UI of
Total Jitter over a short trace for your TX Host then you should be compliant
up to the CIC channel which is at the end of your Host. Â The additional Jitter
you will measure up to your TX host compliant point will be ISI and potential
crosstlak and unless these are unusually large you should be ok. Â The
compliance Jitter is 0.180UI for RJ (MFTP) and 0.340UI (TJ minus RJ with LBP)
at TX Host complaint point. Â Now if Altera did not provide a Jitter profile
then you could back the measured Jitter profile into you Your IBIS AMI or
Hspice model. Remember to include the package in your analysis as this will
contribute to the ISI and potential crosstalk noise you might be encountering.
 With 32ps of Jitter I would venture to say you have roughly 20ps of  RJ and
12ps of DJ which will be DCD/PJ and whatever your path produces for
ISI/Crosstalk. Â Back the Jitter profile into your simulation model once you
get reasonable correlation then add the rest of the TX Host and check for
compliance. Â With 9dB of insertion loss you will should redrive somewhere near
mid-point on your CIC channel (between TX Host board RX Device Board) since CIC
compliance will fail which is to say about 4.5dB of insertion loss at 3Ghz. Â
There is TX Host after CIC compliance check which will more than likely fail
with the 9dB of insertion loss at 3Ghz but I have seen system pass/work with
6dB of CIC insertion loss and with emphasis/equalization pass with 7.5dB of CIC
insertion loss.To check your RX Device this is a Jitter Tolerance test which is
done in loopback. Â You can of course check your full path EYE but there are no
mask for this.Regards,-Jory From: Zheng Edison <edisonzheng@xxxxxxxx>
To: joel@xxxxxxxxxx; SI-List <si-list@xxxxxxxxxxxxx>
Sent: Sunday, February 15, 2015 5:35 AM
Subject: [SI-LIST] Re: Question about jitter at serdes transmitter
Hi Joel:
The emphasis greatly affects the jitter ,but spice models usually don't include
it.So,I think it is valueless to simulate jitter using spice model.the
measuring data is believable.
--- Original Message ---
From: "Joel Brown" <joel@xxxxxxxxxx>
Sent: February 13, 2015 8:26 AM
To: "SI-List" <si-list@xxxxxxxxxxxxx>
Subject: [SI-LIST] Question about jitter at serdes transmitter
We are using an Altera Arria II GX FPGA for a SATA 3 6GBPSÂ interface.
I ran some simulations in Hspice and the amount of jitter in the simulation
is much less than what I measured on the actual system. I decided to
simplify the system by isolating the board with just the FPGA on it and
terminating the trace with a 100 ohm 0201 resistor. The differential trace
is about 1.5 inches long and runs on a single surface layer. My simulation
shows about 1.6 db loss at 3 GHz which is about what I am measuring on the
scope. When I look at the output of the FPGA I already see about 32 ps of
jitter (0.2 UI) and it seems to be data pattern related. Is this a normal
amount of jitter to expect at the output of a serdes transmitter? In the
actual system the signal runs across five boards and four connectors before
arriving at a redriver and by then its pretty hosed. The simulated loss is
about 9 db.
Thanks - Joel
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