[SI-LIST] Re: Question about jitter at serdes transmitter
- From: Zheng Edison <edisonzheng@xxxxxxxx>
- To: <joel@xxxxxxxxxx>, SI-List <si-list@xxxxxxxxxxxxx>
- Date: Sun, 15 Feb 2015 18:35:17 +0800
Hi Joel:
The emphasis greatly affects the jitter ,but spice models usually don't include
it.So,I think it is valueless to simulate jitter using spice model.the
measuring data is believable.
--- Original Message ---
From: "Joel Brown" <joel@xxxxxxxxxx>
Sent: February 13, 2015 8:26 AM
To: "SI-List" <si-list@xxxxxxxxxxxxx>
Subject: [SI-LIST] Question about jitter at serdes transmitter
We are using an Altera Arria II GX FPGA for a SATA 3 6GBPS interface.
I ran some simulations in Hspice and the amount of jitter in the simulation
is much less than what I measured on the actual system. I decided to
simplify the system by isolating the board with just the FPGA on it and
terminating the trace with a 100 ohm 0201 resistor. The differential trace
is about 1.5 inches long and runs on a single surface layer. My simulation
shows about 1.6 db loss at 3 GHz which is about what I am measuring on the
scope. When I look at the output of the FPGA I already see about 32 ps of
jitter (0.2 UI) and it seems to be data pattern related. Is this a normal
amount of jitter to expect at the output of a serdes transmitter? In the
actual system the signal runs across five boards and four connectors before
arriving at a redriver and by then its pretty hosed. The simulated loss is
about 9 db.
Thanks - Joel
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