[SI-LIST] Re: Question about jitter at serdes transmitter
- From: David Banas <capn.freako@xxxxxxxxx>
- To: joel@xxxxxxxxxx
- Date: Fri, 13 Feb 2015 07:01:08 -0800
Hi Joel,
> ran some simulations in Hspice and the amount of jitter in the simulation
> is much less than what I measured on the actual system.
Typically, Tx output jitter is NOT included in the default SPICE models from
silicon vendors. Have you checked to see if the model youre working with
includes it? I suspect it does not.
> When I look at the output of the FPGA I already see about 32 ps of
> jitter (0.2 UI) and it seems to be data pattern related. Is this a normal
> amount of jitter to expect at the output of a serdes transmitter?
Yes, this is normal. Typical link jitter budgeting (at least, below 10 Gbps) is
done, rather simplistically, as: 0.3UI, 0.3UI, 0.3UI (Tx, channel, Rx). The
last 0.1UI is your safety margin.
-db
On Feb 12, 2015, at 4:25 PM, Joel Brown <joel@xxxxxxxxxx> wrote:
> We are using an Altera Arria II GX FPGA for a SATA 3 6GBPS interface.
> I ran some simulations in Hspice and the amount of jitter in the simulation
> is much less than what I measured on the actual system. I decided to
> simplify the system by isolating the board with just the FPGA on it and
> terminating the trace with a 100 ohm 0201 resistor. The differential trace
> is about 1.5 inches long and runs on a single surface layer. My simulation
> shows about 1.6 db loss at 3 GHz which is about what I am measuring on the
> scope. When I look at the output of the FPGA I already see about 32 ps of
> jitter (0.2 UI) and it seems to be data pattern related. Is this a normal
> amount of jitter to expect at the output of a serdes transmitter? In the
> actual system the signal runs across five boards and four connectors before
> arriving at a redriver and by then its pretty hosed. The simulated loss is
> about 9 db.
> Thanks - Joel
>
>
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