[SI-LIST] Re: Question about jitter at serdes transmitter
- From: "Iliya Zamek" <dmarc-noreply@xxxxxxxxxxxxx> (Redacted sender "i_zamek@xxxxxxxxx" for DMARC)
- To: "joel@xxxxxxxxxx" <joel@xxxxxxxxxx>, SI-List <si-list@xxxxxxxxxxxxx>
- Date: Fri, 13 Feb 2015 02:56:23 +0000 (UTC)
Hello Joel,Â
There are many effects that contribute to the Transmitter jitter. Among them
Jitter due to ISI and channel' losses that you were considered. PDN induced is
another source of Jitter. This Jitter component in a system of Chip-Package-PCB
is often overlooked, while the value that it might bring is often dominates all
other Jitter components.
You might want to see the measurement results of this type of Jitter in FPGA
here:Â
http://www.semtech.com/power-management/On-Chip-Jitter-and-System-Power-Integrity.pdf
Also, you might want to see recently published DesignCon 2015 Tutorial on this
part of Jitter (see part 3): Â
http://www.designcon.com/santaclara/scheduler/session/system-power-integrity
Thank you. Iliya
On Thursday, February 12, 2015 4:27 PM, Joel Brown <joel@xxxxxxxxxx> wrote:
We are using an Altera Arria II GX FPGA for a SATA 3 6GBPSÂ interface.
I ran some simulations in Hspice and the amount of jitter in the simulation
is much less than what I measured on the actual system. I decided to
simplify the system by isolating the board with just the FPGA on it and
terminating the trace with a 100 ohm 0201 resistor. The differential trace
is about 1.5 inches long and runs on a single surface layer. My simulation
shows about 1.6 db loss at 3 GHz which is about what I am measuring on the
scope. When I look at the output of the FPGA I already see about 32 ps of
jitter (0.2 UI) and it seems to be data pattern related. Is this a normal
amount of jitter to expect at the output of a serdes transmitter? In the
actual system the signal runs across five boards and four connectors before
arriving at a redriver and by then its pretty hosed. The simulated loss is
about 9 db.
Thanks - Joel
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