[SI-LIST] Query on ddr2 layout guidelines

  • From: "umashankar subramaniam" <shankarums@xxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Fri, 9 May 2008 00:09:28 +0530

Hi
I just want to know difference between ddr/ddr2/ddr3 layout instructions.
are these differ based on application or with type of board?
send me instructions that truly describe these devices layout guidelines.

I am using ddr2 in my credence template board for DTV/video applications.
I found that trace width that i received in stack up has 6mils-50ohm, 5/6/5
for 100ohms for microstrip traces(top&bot)
since we kept decaps under DDR2 pins in bot, we are getting 3mils clearance
between traces while routing from dut to DDR2.
Can we neck down 50 ohm traces inside the DDR* footprint? should it affect
the performance of ddr*.
i am just confused on this.

Also tell me should we need to include via stub length in length report?
is the via stub length is applicable for lvds, hdmi diff pair traces too?
-- 
Regards
------------
Umashankar Subramaniam,
Application Engineer


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