Hi Techies, I have a question on Eye-diagram. We are having an interface between ADC and Virtex-5 FPGA. this interface is High-Speed differential interface. Iam simulating the interface with Hyper Lynx BoardSim. I want to know What are the things i need to look up in the simulation so that i can say my layout is fine? I have generated an eye-diagram using HyperLynx but what exactly it will tell. As far as my knowledge is concerned an eye-diagram can't tell us that our impedance matching and our layout is correct. Correct me if iam wrong. Can you just share me your thoughts on what to observe. Iam new to SI tool and analysis so please help me in this. Iam also attaching my simulation results with this mail. Please let me know how to add files as this group is not allowing pictures to be shared. Thanks & Regards Srikanth Chundi ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu