[SI-LIST] Re: Query about Hyperlynx tool

  • From: "Zabinski, Patrick" <zabinski.patrick@xxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Fri, 5 Mar 2010 05:39:26 -0600

Chundi,

The short answer is that the three models attempt to represent the
variation you can expect in performance across all the chips, and you
should be using all of the models.

A longer answer begins with a description of what these models
represent.  In brief, IC fabrication is not absolutely exact.  All the
etching, imaging, and doping processes have some small amount of
variation.  The variation exists between fabrication lots, within a
single wafer, and even within each IC.  

The physical variations result in electrical variations in performance.
Each transistor on an IC behaves slightly different than the transistor
next to it.  Generally, the variation on a single IC is small, but it
does exist.  For large production ICs that are fabricated over several
wafer lots over differetn days, weeks, months, or years, the variation
can get large.

Electrically, the variation manifests itself in all kinds of ways.  The
parasitic capacitances are way, as you suggest. But other things happen
as well, such as the gain, resistance, leakage, etc.  Considering an
HSPICE transistor model with all its parameters, nearly every one of
those parameters has some amount of variation in performance due to the
manufacturing tolerance.

Beyond fabrication tolerance, the models often also try to account for
voltage variations and temperature extremes.  So, if you have a 1.0 V IC
with a 10% voltage tolerance, the slow model often represents the
performance of the IC when 900 mV is appplied, etc.

It is impractical to provide models to people that account for every
possible variation.  Instead, manufacturers simplify the variations by
offering three representative cases: slow, typical, fast (or weak,
typical, strong).  These models do not exactly represent what you will
see in all your ICs, but they come reasonably close.

If you take a detailed look in the lab at any IC, it will not perform
exactly as indicated by a "typical" model, but it should come close.  If
you then take another IC, it too will come close, but it will behave
differently.  If you take many such Ics in the lab, measure them, and
compare them to the models, all the ICs should perform within the range
indicated by the slow/typical/fast models.

So, if you are trying to develop a robust system that will operate with
any of the ICs you are likely to get, then you should be running your
simulations with all the models variations.

As Steve indicates, though, typical models are a great place to start
for SI analysis.  We commonly use the typical models to make decisions
about terminations, trace design issues, etc.  Once we get reasonable
performance using the typical models, we then run a matrix of
simualations that use an assortment of slow, typical, and fast models
and make sure everything still works.  In many cases, the inclusion of
these model extremes breaks the link whereby we no longer meet margin,
and we are forced to adjust our design.

Good luck.

Pat Zabinski
Mayo Clinic



-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of chundi srikanth
Sent: Friday, March 05, 2010 5:16 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Query about Hyperlynx tool

Hi All,
Iam using Hyperlynx Boardsim tool. I have a query on this tool. There is
provision in the tool to select the IC modelling like slow-week,typical
and fast-strong modelling. So as far as my knowledge is concerned these
modellings vary on the basis of RC parasitics. I would like know whether
my assumption is correct? And generally which modelling we need to
select and what basis we need to select this for single-ended and
differential high-speed signal simulations.

Thanks
Chundi


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