[SI-LIST] Query Regarding DQS line in DDR-SDRAM's

  • From: Raghavendra <raghavendra@xxxxxxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Tue, 24 Aug 2004 19:31:13 +0530

Hi Guys,
     I had a query regarding the DQS lines in DDR-SDRAM.

As we know, most 16 bit wide DDR-SDRAM's provide 2 separate DQS (Data 
Strobe) lines for strobing the higher and the lower bytes respectively 
and these are I/O lines( is an input to SDRAM for writes to it and is an 
output from SDRAM for reads from it) . We are designing a DDR-SDRAM 
controller for 16-bit wide memories but due to shortage of pins want to 
provide only one DQS line from the controller for strobing these 16-bits 
of Data. For this we want to short both the LDQS and UDQS on the 
DDR-SDRAM side. When this signal is an input to the SDRAM, there is no 
problem but when the SDRAM is driving out the Data (for reads from  
SDRAM), both these lines will be asserted. Also the datasheet says that 
there could be a maximum skew of  500ps between the LDQS and UDQS. My 
concern is whether this shorting of two actively driven outputs will any 
problems on the board and on the reliability of the device. It is 
ensured that these lines will be driving the same logic level at any 
point of time with a  maximum skew of 500ps, which means there could be 
a short for 500ps(assuming UDQS is low and LDQS is high) during reads 
from SDRAM.

Will there be any long term problems with this arrangement or is it 
mandatory to provide separate lines from the controller for this ?? Also 
can this problem be handled by providing resistors on these lines before 
the shorting so that it does not become a dead short. The pads of the 
DDR-SDRAM are of the type SSTL2, Class II and we want to operate at a 
clock of 166MHz ( data rate of 333MHz). Please comment.

Thanks and Regards
Raghavendra




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