[SI-LIST] Re: QDR <=> Processor interface
- From: Knut Georg Wiljugrein <kwiljugrein@xxxxxxxxx>
- To: igazula@xxxxxxxxxxx
- Date: Thu, 21 Jul 2005 15:43:17 +0200
Hi Indira,
I've recently made a QDR-II Interface for a FPGA, and one thing you
might have to consider is that although the interface is source
synchronous, the CPU will have to re-sample the source synchrounous
read-data back into its internal clock domain.
The phase relationship between the returning clock from the QDR-II RAM
and the internal processor clock is given by the round trip delay from
the processor to the qdr-ii back to the processor. The reason for
specifying the maximum length may be to limit this round trip delay in
order to bound the phase difference.
If any phase relationship (i.e. any trace length) is allowed the there
is no way to guarantee setup and hold times for the re-sampling of
read-data from the source synchronous clock domain into the internal
clock domain, and the CPU would have to implement full clock domain
transition logic (asynch FIFO etc.) to receive read-data without
meta-stability problems. With a bounded phase difference, setup and hold
times can be guaranteed, and the data is simply re-sampled in a simple
flip-flop without getting meta-stability problems.
You should probably check the CPU data sheet for any timing constraints
between the returned QDR-II read clock with regards to the internal
clock or QDR-II output clock and see if this may give sense to the
3000mil length limitation.
Best Regards,
Knut Georg Wiljugrein
Indira Gazula wrote:
>Hi Dagmara,
>
>Thanks for the feedback. What I forgot to mention earlier is that it is source
>sync interface and is meeting the timing constraints (set-up and hold
>margins)even for longer lengths. There is no particular limit on propogation
>delay. Considering this, what would you say is limiting the length?
>
>Indira.
>Dagmara Avanindra <dagmara.avanindra@xxxxxxxxx> wrote:
>Indira,
>
>when deceiding upon the trace length, it is important to remember not
>just the quality of the signal (clean rise time, voltage margin) but
>also timing constraints. You need to take into account propogation
>delay into your timing margin. Look at the timing spec of the
>interface, and perhaps that will make more sense on length constraint.
>
>The shunt resistor is there to kill off reflections, for having
>reflections can break a tight timing interface. You can get rid of the
>resistors in your simulation, and see the difference. If your
>microprocessor has well-controlled output impedance, there may be a
>chance that you can get away without the termination resistors. But
>you need to do simulations to confirm that.
>
>Thanks,
>Dagmara
>
>
>
>On 7/20/05, Indira Gazula wrote:
>
>
>>Hi All,
>>
>>I have recently stepped into the world of SI and would appreciate any inputs
>>on my question:
>>
>>I am working on the interface between a QDR-II SRAM and Processor (163 Hz
>>clock, 1.5V). The suggestions for this interface is that trace length should
>>not exceed ~3000mil. This particular interface has a shunt resistor of 50Ohm
>>to 0.75V on the QDR side. Simulations suggest longer trace lengths give
>>acceptable performance for much longer trace lengths. Could anyone please
>>explain why it is suggested that trace lenght should be restricted to 3in,
>>also how it would be different if there is no shunt termination (is it
>>required).
>>
>>Thanks in advance for the help.
>>
>>Best Regards,
>>
>>Indira.
>>
>>
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