[SI-LIST] Re: Problems with system bus design
- From: kellee <kellee@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Sun, 25 Jan 2004 13:40:47 -0800
It is more likely the vendor's Ioh data takes other details into account.
The formula is only valid if the vendor's Voh and Ioh values
are the from the actual load line of the output during the
transition. Some vendors publish Ioh values that are less
than the load line of the output to insure the ground and
power structure can sustain the DC and transient
current needed for all outputs. In addition many outputs
today use variable output drive stages so the DC
Ioh value does not have to match the transient value.
best regards,
Kellee
----- Original Message -----
>From: "pom gud" <pomgud@xxxxxxxxx>
>To: <si-list@xxxxxxxxxxxxx>
>Sent: Sunday, January 25, 2004 4:33 AM
>Subject: [SI-LIST] Problems with system bus design
>
>
> > Hello,
> > I am using a 32-bitprocessor in current design.
> > I have one technical doubt about system bus design.
> > In processor data sheet, in DC Electrical
> > Specification section, it is mentioned that drive
> > capability of data bus is 6 mA and output load is of
> > 30 pF. I am referring a book "High Speed Digital
> > Design; A hand book of Black Magic" by Howard Johnson
> > for peripheral bus analysis. As per formulas given in
> > this book i found that it is not possible for
> > processor peripheral data bus to drive 30 pF load with
> > 6 mA drive capability and meet rise time requirement
> > of 1.5 nS. The design calculations are as follows,
> >
> > Output driver resistance = (VCC- VOH)/IOH =
> > (3.3 - 2.4)/ 6 mA = 150 ohm
> > So rise time = 2.2*R*C = 2.2*150*30pF
> > = 9.9 nS
> >
> > I have a lot of confusion about these calculations.
> >
> > Hoping for a quick reply
> >
> > Thanks and Regards
> > pomgud
> >
> >
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