[SI-LIST] Re: Practical Analysis Of Backplane Vias

  • From: Conrad Herse <herse@xxxxxxxxxxxxxxxxxx>
  • To: Aubrey Sparkman <asparkman@xxxxxxxxxxxxx>
  • Date: Fri, 03 Apr 2009 13:01:08 -0500

A paper with a virtually identical title and co-authored by Dr. Bogatin 
was presented at DesignCon 2009 (7-TA2). I'm not sure how to get access 
to the DesignCon papers if you did not attend, check with your colleagues.

Conrad Herse

Aubrey Sparkman wrote:
> Colin,
> 
> RF Global Net requires me to fill out yet another signup sheet.  Is this
> paper available from another source?  Or is RF Global Net a source you
> highly recommend?
> 
> Thanks,
> Aubrey Sparkman
> Aubrey.K.Sparkman@xxxxxxxx
> 
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
> Behalf Of colin_warwick@xxxxxxxxxxx
> Sent: Friday, April 03, 2009 10:54 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Practical Analysis Of Backplane Vias
> 
> Hi,
>  
> 
> RF Global Net are offering a download of a white paper that my Agilent
> colleagues Sanjeev Gupta and Mike Resso co-wrote with Eric Bogatin (Bogatin
> Enterprises) and Lambert Simonovich (Nortel):
> 
>  
> 
> "Practical Analysis Of Backplane Vias"
> 
>  
> 
> In this paper, Dr. Bogatin and his co-authors show how accurate, verified
> models for vias in a multilayer circuit board are necessary to predict link
> performance in the multi-gigabit-per-second regime. It describes a method
> for using measurements on a test vehicle to build a high-bandwidth, scalable
> model of long vias, including the through- and stub-effects. This model can
> then be used in Agilent's Advanced Design System for simulation. The
> methodology provides valuable insight into the root causes of performance
> limits and how to overcome them.
> 
> http://www.rfglobalnet.com/download.mvc/Practical-Analysis-Of-Backplane-Vias
> -0001  
> 
>  
> 
> Enjoy!
> 
>  
> 
> -- Colin
> 
> http://signal-integrity-tips.com <http://signal-integrity-tips.com/>  
> 
>  
> 
> 
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