[SI-LIST] Re: Power plane coupling
- From: "Larry Smith" <LSMITH@xxxxxxxxxx>
- To: <ludovic.levieil@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 21 Oct 2005 12:04:31 -0700
Ludovic - I like this power plane stackup sequence, particularly if it
is on the top or bottom surface of the PCB.
The power planes will be highly coupled to ground by discrete decoupling
capacitors mounted on the surface of the board. There are probably
100's of uF that are trying to maintain a constant voltage between VCC1
and Gnd, also between VCC2 and Gnd. But the internal plane to plane
capacitance is on the order of 1nF, not much compared to the external
capacitance. At 100MHz, the 1 nF plane-to-plane impedance is about
1/(2*pi*100e+6*1e-9) =3D 1.59 Ohms. This is not strong compared to the
impedance of the PDS which is probably in the mOhms. The impedance
division insures that there will not be substantial noise coupled from
one power plane to the other in this stackup. But as Istvan has
commented in another note on this thread, this might not be best for a
sensitive analog supply or PLL circuitry. Further filtering should be
used for those supplies.
Noise above 100 MHz usually gets onto a power plane because of
transmission line return current. I like your stackup because the power
planes are surrounded by Gnd planes. You have an opportunity for
transmission lines to reference only ground planes throughout the rest
of the stackup. This keeps the return current noise off the power
planes and the power plane noise off the transmission lines. Skin
effect in solid ground planes greatly attenuates magnetic fields from
penetrating through the planes at 1 MHz and above.
Noise below 100 MHz is usually caused by current transients from the
loads. A well designed PDS will be below target impedance from some
corner frequency (50 to 100 MHz) all the way down to DC. The noise
coupled between power planes below this corner frequency is diminished
because the impedance of the plane-to-plane capacitance diminishes at
lower frequency. This stackup puts you well on the way towards good
power and signal integrity in your product.
Regards,
Larry Smith
Altera Corporation
(Sun Microsystems was very good for me, but it was time to move on.)
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Ludovic Levieil
Sent: Thursday, October 20, 2005 1:12 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Power plane coupling
Hello All,
In my current board design I have the following stack up:
.......
---------------- GND (solid plane)
------ ----- --- VCC1 (splitted plane)
--- ----- ------ VCC2 (splitted plane)
---------------- GND (solid plane)
.......
4 mils separate GND and VCC planes
5 mils separate VCC1 and VCC2 planes
Both VCC planes are splitted in different power domains and I am
wondering=20
:
- if having two coupled VCC planes is good/acceptable when=20
thinking about noise ??
- if there is a problem in having one power domain on on plane=20
overlapping at least two power domains on the other plane ??
Thanks
Ludovic Levieil=20
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=20
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