[SI-LIST] Re: Power plane / VCC plane as reference for differencial microstrips
- From: steve weir <weirsp@xxxxxxxxxx>
- To: niki@xxxxxxxxxxxxxx, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 20 Aug 2004 01:58:27 -0700
Niki, in a perfect world, the return current from each half of the
differential pair is equal and opposite. This results in a net transverse
current between the pairs in the return. If you had a split that is small
compared to your signal content, then your description is fairly
reasonable, under the assumption of perfectly balanced signaling.
Now for the problems:
Even without the split, the common mode signal content is going to excite
the resonant cavity formed by your Vcc and ground planes. That's some
pretty high frequency stuff, ( 600Mbps = 1.6ns / cell about 100-200ps Tr =
1.5-3GHz knee ), so this is an invitation to expensive EMC fixes, like a
bullet proof case, or thin dielectrics. If your VCC islands are large,
even thin dielectrics will be of limited help due to the board 1/2 wave
resonances.
With the plane splits, your CM has to find a new path, that is generally
going to be through the plane to ground capacitance of each island. At the
same time, the DM coupling in the region of the split will jump up, and you
will have an impedance discontinuity.
If you can avoid the topology you describe and reference the LVDS to only
ground, your life will be easier. If not, you have a job in front of you
that calls for modelling. If you are going to try to wing it, get some
seriously low inductance capacitors to bridge the planes. Either X2Y, or
IDC. are the best choices. However, you need to realize that the mounted
inductance of those devices is going to still present a substantial
impedance bump for signals with 100ps rise times. This thing is going to
want to radiate.
Steve.
At 10:27 AM 8/20/2004 +0200, Niki Steenkamp wrote:
>Hi,
>
>I have a six layer board that contains LVDS (up to 600mbps) traces on =
>both
>outer layers. The top layer uses the solid ground plane beneath it as
>reference plane, while the bottom layer uses the split VCC plane as a
>reference plane. I am worried about the bottom LVDS layer since the =
>LVDS
>traces have to run over two different VCC planes. If the transmission =
>lines
>where single ended (as opposed to differential), I would have had to =
>make
>sure the there is a low impedance path for the return current to cross =
>from
>the one VCC plane to the other (using decoupling caps close to the =
>crossover
>point, for instance), but since I am using differential signalling, =
>there
>should be (in theory at least) no net return current. The (equal and
>opposite) return currents below each microstrip would simply "loop back" =
>when
>they reached the break in the reference plane and a new return current =
>loop
>will be created in the next plane. Am I understanding this correctly? =
>I can
>think of two real-world complications: the one is the finite break width
>(where there is no reference plane, except the ground plane which is a =
>lot
>further away). The other is the imbalance in the LVDS drivers, making =
>the
>signal not perfrectly differential. I do not really have a feeling for =
>this,
>is it something to worry about? Can I expect a signicant reduction in =
>signal
>quality?
>
>I am unfortunately only a lowly digital design engineer, so my =
>understanding
>of the high frequency aspects are, well, limited at best! Any feedback =
>from
>the pros would be welcome!
>
>Regards,
>Niki
>=20
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