[SI-LIST] Re: Power module

  • From: "massoud shakeri" <massoud@xxxxxxxxxxx>
  • To: <6rahulrajendran@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
  • Date: Sun, 3 Jun 2012 23:58:35 -0700

Hi Rahul,
The main reason for this is because of Simultaneously Switching Outputs.
Imagine all or most of the address lines or Data lines to go from 0 to 1 or
from 1 to 0 simultaneously, which can happen frequently in memory modules.
If each output needs 20ma to 30ma during the rise time for transition, your
power source must be able to deliver a few amperes of switching current in
that short time, without any change in the output voltage. 
Power Delivery System (PDS) design for DDR3 is not a trivial thing:
    - If the rise time is < 2 nS  this current must be supplied over a
frequency band from  DC to > 1GHz to both work correctly and to avoid
becoming a Common Mode EMI source.
   - Power Delivery System must have a source impedance of  0.1 ohms or
less, over that frequency band, otherwise the power rails move more than the
noise budget, acceptable for the system.
I think there are lots of things to consider for designing a working PDS.
Just for start, there are several free tools to calculate the combination of
capacitors you need to have such a low source impedance. But eventually
after selection of capacitors and their placement on board, you need to
simulate the whole PDS to make sure it can deliver the power, without Ground
Bounce.

Massoud Shakeri


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Rahul Rajendran
Sent: June-03-12 10:19 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Power module

Hi,
 I have to choose some power modules for my board. My point is when ever i
have looked up boards they have used power modules with more current than
the maximum current requirement for the target module. Say for example , If
i want provide a module for RAM , DDR3 UDIMM , the typical ratings are 1.5 V
and 3 A. But the modules used have been designed to give more current.
Can some one give a reason for this over design. And how much percentage
should we over estimate the max current value



Rahul R


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