[SI-LIST] Re: Power integrity / Transient current in Target impedance
- From: Raymond Anderson <Raymond.Anderson@xxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 11 Dec 2003 09:08:13 -0800
A few generic comments on 'I_transient' :
The equation cited for determining the target impedance is indeed rather
straight forward, and the parameters are for the most part fairly easy to
determine except for the 'I_transient' number.
The transient current can vary considerably depending on the component type
and technology. For example, ECL parts have a relatively constant current
draw and exhibit very low transient currents. Typical CMOS parts might be
rationalized to have a transient current around 50% of Imax. Memory
parts can
have up to 80% or so transient current demands. Microprocessors are a bit
more difficult to generalize. The transient current depends on the
technology, the internal architecture, and how the part is used. (is Energy
Star standby enabled and how does the part 'wake-up'?, does the pipelineing
architecture 'even-out' process loading or are their periods of inactivity
followed by periods of intensive activity?, etc., etc. .....). Application
s/w can also alter the transient demands. For the purpose of the target Z
equation you really want to determine the worst-case transient demands.
I've seen processors exhibit transient current requirements ranging from
about 10% to 50% of Imax. Measurement of this current can be most
challenging (if at all possible in some cases).
You will in all likelyhood NOT find the transient current demand for a chip
directly listed in a parts datasheet. For some parts you may be able to
estimate the number by inference from other published specs, but in the case
of processors and complex ASICS this is most likely not the case. Measured
values are the best data you will come by, but as previously stated, in some
cases the measurement is not at all easy.
For some power distribution architectures you _might_ be able to clamp
a current probe on a Vdd supply wire and read the transient current on a
scope, but in more advanced pds architectures where every effort is made to
reduce the inductance between the VRM and the load this probably isn't
possible to do as all the currents are flowing on plane pairs with no
clampable wires existing. You might be able to measure a voltage drop
across a low value of resistance but the accuracy of this would depend of
having an accurately know resistance in series with the current flow.
(not usually the case, nor desired...).
-Ray Anderson
Sun Microsystems Inc.
Saeed Bakhshi wrote:
>Hi
>
>I have reviewed all si-list threads regarding to power integrity and
>decoupling cap selection. all have said that there must be a target impedance
>and this target impedance should be met up to several harmonics of existing
>clocks frequencies ; and the target impedance is calculated using the below
>equation:
>Target impedance= VDD x (Voltage tolerance) / "I_transient"
>
>OK, But nobody explain how "I_transient" value could be calculated.
>
> In all datasheets there is a ICC(current drawn from power supply) in absolute
> maximum rating table. Is this ICC the same "I_transient"? or a fraction of
> ICC should be used as "I_transient"?
>
> What is the relationship between ICC mentioned in the "Absolute maximum
> rating table of Chip datasheets" and the "I_transient" in target impedance
> formula?
>any comment is appreciated.
>
>
>Regards,
>Saeed Bakhshi
>
>
>
>
>
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